公开(公告)号：US09153483B2

公开(公告)日：2015-10-06

申请号：US14066889

申请日：2013-10-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Wen-Hung Tseng ,  Hung-Chang Hsieh

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/423 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28141 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/4763 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76879 ,  H01L21/7688 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 提供了第一导电特征和第二导电特征。 在第一导电特征上形成第一硬掩模（HM）。 在第一和第二导电特征上形成图案化的介电层，其中第一开口露出第二导电特征。 第一金属插塞形成在第一开口中以接触第二导电特征。 在第一金属插塞上形成第二HM，并且在衬底上方形成另一图形化的电介质层，其中第二开口露出第一金属插塞和第一导电特征的子集。 在第二开口中形成第二金属塞。

公开(公告)号：US20140255850A1

公开(公告)日：2014-09-11

申请号：US13791992

申请日：2013-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ching-Yu Chang ,  Ming-Feng Shieh ,  Wen-Hung Tseng

IPC: G03F7/004

CPC classification number: G03F7/0045 ,  G03F7/004 ,  G03F7/0046 ,  G03F7/0392 ,  G03F7/30 ,  G03F7/32 ,  H01L21/0274

Abstract: A method for fabricating a semiconductor product includes applying a photo-resist layer to a substrate, the photo-resist layer including a higher acid concentration at an upper portion of the photo-resist layer than at a lower portion of the photo-resist layer. The method also includes exposing the photo-resist layer to a light source through a mask including a feature, the photo-resist layer including a floating, diffusing acid that will diffuse into a region of the photo-resist layer affected by the feature while not diffusing into a feature formed by the mask.

Abstract translation: 一种制造半导体产品的方法包括将光致抗蚀剂层施加到基底上，所述光致抗蚀剂层在光致抗蚀剂层的上部比在光致抗蚀剂层的下部具有更高的酸浓度。 该方法还包括通过包括特征的掩模将光致抗蚀剂层暴露于光源，该光致抗蚀剂层包括将扩散到受特征影响的光致抗蚀剂层的区域中的浮动扩散酸，而不是 扩散到由掩模形成的特征中。

公开(公告)号：US20140252433A1

公开(公告)日：2014-09-11

申请号：US13911183

申请日：2013-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd .

Inventor： Ming-Feng Shieh ,  Wen-Hung Tseng ,  Chih-Ming Lai ,  Ken-Hsien Hsieh ,  Tsai-Sheng Gau ,  Ru-Gun Liu

IPC: H01L21/283 ,  H01L29/40

CPC classification number: H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41725

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract translation: 一种用于在半导体器件内形成金属触点的方法包括：将第一层触点形成为围绕至少一个栅电极的第一电介质层，第一层触点延伸到下面的衬底的掺杂区域。 该方法还包括在第一电介质层上形成第二电介质层，并形成延伸穿过第二电介质层的第二层接触到第一层接触。

公开(公告)号：US11735477B2

公开(公告)日：2023-08-22

申请号：US16880718

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Hung-Chang Hsieh ,  Wen-Hung Tseng

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L23/485 ,  H01L21/4763 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28141 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/7688 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53233 ,  H01L23/53257 ,  H01L27/0924 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L21/31055 ,  H01L21/4763 ,  H01L21/76852 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823828 ,  H01L23/53295 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

公开(公告)号：US20190051564A1

公开(公告)日：2019-02-14

申请号：US16153956

申请日：2018-10-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Wen-Hung Tseng ,  Tzung-Hua Lin ,  Hung-Chang Hsieh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L21/311

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

公开(公告)号：US10096519B2

公开(公告)日：2018-10-09

申请号：US15257469

申请日：2016-09-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Wen-Hung Tseng ,  Tzung-Hua Lin ,  Hung-Chang Hsieh

IPC: H01L21/76 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

公开(公告)号：US20160254183A1

公开(公告)日：2016-09-01

申请号：US15149500

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Wen-Hung Tseng ,  Chih-Ming Lai ,  Ken-Hsien Hsieh ,  Tsai-Sheng Gau ,  Ru-Gun Liu

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41725

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract translation: 一种用于在半导体器件内形成金属触点的方法包括：将第一层触点形成为围绕至少一个栅电极的第一电介质层，第一层触点延伸到下面的衬底的掺杂区域。 该方法还包括在第一电介质层上形成第二电介质层，并形成延伸穿过第二电介质层的第二层接触到第一层接触。

公开(公告)号：US09337083B2

公开(公告)日：2016-05-10

申请号：US13911183

申请日：2013-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Wen-Hung Tseng ,  Chih-Ming Lai ,  Ken-Hsien Hsieh ,  Tsai-Sheng Gau ,  Ru-Gun Liu

IPC: H01L21/283 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41725

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract translation: 一种用于在半导体器件内形成金属触点的方法包括：将第一层触点形成为围绕至少一个栅电极的第一电介质层，第一层触点延伸到下面的衬底的掺杂区域。 该方法还包括在第一电介质层上形成第二电介质层，并形成延伸穿过第二电介质层的第二层接触到第一层接触。

公开(公告)号：US20160027692A1

公开(公告)日：2016-01-28

申请号：US14875535

申请日：2015-10-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Feng Shieh ,  Hung-Chang Hsieh ,  Wen-Hung Tseng

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/308

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 提供了第一导电特征和第二导电特征。 在第一导电特征上形成第一硬掩模（HM）。 在第一和第二导电特征上形成图案化的介电层，其中第一开口露出第二导电特征。 第一金属插塞形成在第一开口中以接触第二导电特征。 在第一金属插塞上形成第二HM，并且在衬底上方形成另一图形化的电介质层，其中第二开口露出第一金属插塞和第一导电特征的子集。 在第二开口中形成第二金属塞。

公开(公告)号：US20150132702A1

公开(公告)日：2015-05-14

申请号：US14599048

申请日：2015-01-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Yu Chang ,  Ming-Feng Shieh ,  Wen-Hung Tseng

IPC: G03F7/004 ,  G03F7/30 ,  H01L21/027

CPC classification number: G03F7/0045 ,  G03F7/004 ,  G03F7/0046 ,  G03F7/0392 ,  G03F7/30 ,  G03F7/32 ,  H01L21/0274

Abstract: A method for fabricating a semiconductor product includes applying a photo-resist layer to a substrate, the photo-resist layer including a higher acid concentration at an upper portion of the photo-resist layer than at a lower portion of the photo-resist layer. The method also includes exposing the photo-resist layer to a light source through a mask including a feature, the photo-resist layer including a floating, diffusing acid that will diffuse into a region of the photo-resist layer affected by the feature while not diffusing into a feature formed by the mask.

Abstract translation: 一种制造半导体产品的方法包括将光致抗蚀剂层施加到基底上，所述光致抗蚀剂层在光致抗蚀剂层的上部比在光致抗蚀剂层的下部具有更高的酸浓度。 该方法还包括通过包括特征的掩模将光致抗蚀剂层暴露于光源，该光致抗蚀剂层包括将扩散到受特征影响的光致抗蚀剂层的区域中的浮动扩散酸，而不是 扩散到由掩模形成的特征中。