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公开(公告)号：US20190244921A1
公开(公告)日：2019-08-08
申请号：US16390218
申请日：2019-04-22
发明人： Chin-Wei Kuo , Hsiao-Tsung Yen , Min-Chie Jeng , Yu-Ling Lin
IPC分类号： H01L23/00 , H01L23/498 , H01L23/522 , H01L21/56 , H01L25/065 , H01L23/66 , H01L23/525
CPC分类号： H01L24/11 , H01L21/563 , H01L23/49811 , H01L23/49822 , H01L23/5225 , H01L23/525 , H01L23/53223 , H01L23/53238 , H01L23/53257 , H01L23/5329 , H01L23/66 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2223/6627 , H01L2924/0002 , H01L2924/01028 , H01L2924/01029 , H01L2924/014 , H01P5/028 , Y10T29/49124 , H01L2924/0001 , H01L2924/00
摘要： Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.
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公开(公告)号：US09960133B2
公开(公告)日：2018-05-01
申请号：US15238520
申请日：2016-08-16
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
CPC分类号： H01L24/11 , H01L24/10 , H01L24/15 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/023 , H01L2224/03 , H01L2224/13147 , H01L2224/81815 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
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公开(公告)号：US20170140867A1
公开(公告)日：2017-05-18
申请号：US15419894
申请日：2017-01-30
发明人： Hsiao-Tsung Yen , Huan-Neng Chen , Yu-Ling Lin , Chin-Wei Kuo , Mei-Show Chen , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01F27/28 , H01L23/522
CPC分类号： H01F27/2804 , H01F17/0013 , H01F2017/002 , H01F2017/004 , H01F2027/2809 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
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公开(公告)号：US09633940B2
公开(公告)日：2017-04-25
申请号：US14803205
申请日：2015-07-20
发明人： Hsiao-Tsung Yen , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng , Yu-Ling Lin
IPC分类号： H01L21/02 , H01L23/64 , H01L23/58 , H01F17/00 , H01L23/522 , H01L49/02 , H01L21/768 , H01L23/528 , H01L23/552
CPC分类号： H01L23/5222 , H01F17/0013 , H01L21/76805 , H01L21/76877 , H01L23/5225 , H01L23/5227 , H01L23/528 , H01L23/552 , H01L23/642 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.
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公开(公告)号：US09203146B2
公开(公告)日：2015-12-01
申请号：US14173282
申请日：2014-02-05
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01Q1/38 , H01Q1/50 , H01L23/48 , H01L23/66 , H01L25/065 , H01Q1/22 , H01Q9/04 , H01Q9/14 , G06F17/50 , H01L25/07 , H01Q5/357
CPC分类号： H01Q1/50 , G06F17/5068 , H01L23/48 , H01L23/481 , H01L23/66 , H01L25/0657 , H01L25/074 , H01L2223/6616 , H01L2223/6677 , H01L2225/06531 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/1421 , H01L2924/1461 , H01Q1/2283 , H01Q1/38 , H01Q5/357 , H01Q9/0421 , H01Q9/0442 , H01Q9/145 , Y10T29/49016 , H01L2924/00
摘要： An antenna includes a substrate and a conductive top plate over the substrate. A feed line is connected to the top plate, and the feed line comprises a first through-silicon via (TSV) structure passing through the substrate. The feed line is arranged to carry a radio frequency signal. A method of designing an antenna includes selecting a shape of a top plate, determining a size of the top plate based on an intended signal frequency, and determining, based on the shape of the top plate, a location of each TSV of at least one TSV contacting the top plate. A method of implementing an antenna includes forming a first feed line through a substrate, the first feed line comprising a TSV, and forming a top plate over the substrate, the top plate being electrically conductive and connected to the first feed line.
摘要翻译： 天线包括衬底和衬底上的导电顶板。 馈电线连接到顶板，并且馈电线包括穿过衬底的第一穿透硅通孔（TSV）结构。 馈线布置成携带射频信号。 一种设计天线的方法包括：选择顶板的形状，基于预期的信号频率确定顶板的尺寸，并且基于顶板的形状确定每个TSV的位置至少一个 TSV接触顶板。 一种实现天线的方法包括：通过基板形成第一馈电线，第一馈线包括TSV，以及在衬底上形成顶板，顶板是导电的，并连接到第一馈电线。
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公开(公告)号：US20140327005A1
公开(公告)日：2014-11-06
申请号：US14332090
申请日：2014-07-15
CPC分类号： G01R31/2644 , H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An apparatus for de-embedding through substrate vias is provided. The apparatus may include pads on a first side of a substrate are coupled to through vias extending through a substrate, wherein pairs of the through vias are interconnected by transmission lines of varying lengths along a second side of the substrate. The apparatus may further include pairs of pads coupled together by transmission lines of the same varying lengths. Apparatuses may include through vias surrounding a through via device under test. The surrounding through vias are connected to the through via device under test by a backside metal layer. The apparatus may further include a dummy structure having an area equal to an area of the backside metal layer.
摘要翻译： 提供了一种通过衬底通孔去嵌入的设备。 该设备可以包括在衬底的第一侧上的焊盘通过延伸穿过衬底的通孔耦合，其中通孔对通过沿着衬底的第二侧的不同长度的传输线互连。 该装置还可以包括通过相同变化长度的传输线耦合在一起的成对的焊盘。 装置可以包括围绕通过测试通孔的通孔。 周围通孔通过背面金属层连接到被测试的通孔装置。 该装置还可以包括具有等于背面金属层的面积的面积的虚拟结构。
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公开(公告)号：US10714441B2
公开(公告)日：2020-07-14
申请号：US15946970
申请日：2018-04-06
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
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公开(公告)号：US10269746B2
公开(公告)日：2019-04-23
申请号：US14875448
申请日：2015-10-05
发明人： Chin-Wei Kuo , Hsiao-Tsung Yen , Min-Chie Jeng , Yu-Ling Lin
IPC分类号： H01L21/02 , H01L23/52 , H01L23/00 , H01L23/522 , H01L23/525 , H01L23/498 , H01L23/66 , H01L21/56 , H01L25/065 , H01L23/532 , H01P5/02
摘要： Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.
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公开(公告)号：US09159728B2
公开(公告)日：2015-10-13
申请号：US14528734
申请日：2014-10-30
发明人： Hsiao-Tsung Yen , Yu-Ling Lin
IPC分类号： H01L27/108 , H01L23/528 , H01L23/522 , H01L27/06 , H01L29/06 , H01L49/02 , H01L21/8234 , H01L27/08
CPC分类号： H01L27/10808 , H01L21/823475 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L27/0629 , H01L27/0802 , H01L27/10844 , H01L27/10897 , H01L28/20 , H01L29/0653 , H01L2924/0002 , H01L2924/00
摘要： A system comprises a first transistor comprising a first active region and a second active region, a first resistor comprising a plurality of first vias connected in series, wherein the first resistor is over the first active region, a second resistor comprising a plurality of second vias connected in series, wherein the second resistor is over the second active region, a second transistor comprising a third active region and a fourth active region, a capacitor having a terminal electrically coupled to the fourth active region and a bit line electrically coupled to the third active region.
摘要翻译： 一种系统包括：第一晶体管，包括第一有源区和第二有源区，第一电阻器包括串联连接的多个第一通孔，其中第一电阻器在第一有源区上，第二电阻器包括多个第二通孔 串联连接，其中第二电阻器在第二有源区上方，第二晶体管包括第三有源区和第四有源区，电容器具有电耦合到第四有源区的端子和与第三有源区电耦合的位线 活跃区域。
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公开(公告)号：US20150048432A1
公开(公告)日：2015-02-19
申请号：US14528734
申请日：2014-10-30
发明人： Hsiao-Tsung Yen , Yu-Ling Lin
IPC分类号： H01L27/108 , H01L23/528 , H01L23/522 , H01L27/06 , H01L29/06
CPC分类号： H01L27/10808 , H01L21/823475 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L27/0629 , H01L27/0802 , H01L27/10844 , H01L27/10897 , H01L28/20 , H01L29/0653 , H01L2924/0002 , H01L2924/00
摘要： A system comprises a first transistor comprising a first active region and a second active region, a first resistor comprising a plurality of first vias connected in series, wherein the first resistor is over the first active region, a second resistor comprising a plurality of second vias connected in series, wherein the second resistor is over the second active region, a second transistor comprising a third active region and a fourth active region, a capacitor having a terminal electrically coupled to the fourth active region and a bit line electrically coupled to the third active region.
摘要翻译： 一种系统包括：第一晶体管，包括第一有源区和第二有源区，第一电阻器包括串联连接的多个第一通孔，其中第一电阻器在第一有源区上，第二电阻器包括多个第二通孔 串联连接，其中第二电阻器在第二有源区上方，第二晶体管包括第三有源区和第四有源区，电容器具有电耦合到第四有源区的端子和与第三有源区电耦合的位线 活跃区域。
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