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1.发明申请公开(公告)号：US20160358871A1
公开(公告)日：2016-12-08
申请号：US15238520
申请日：2016-08-16
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
CPC分类号： H01L24/11 , H01L24/10 , H01L24/15 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/023 , H01L2224/03 , H01L2224/13147 , H01L2224/81815 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
摘要翻译： 集成电路封装包括管芯。 导电层包括管芯中的再分配层（RDL），或管芯上方的微凸起层，或两者。 微凸起层包括至少一个微凸起线。 滤波器包括导电层。 电容器包括形成在导电层中的电极。
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公开(公告)号：US20180233471A1
公开(公告)日：2018-08-16
申请号：US15946970
申请日：2018-04-06
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
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公开(公告)号：US09059026B2
公开(公告)日：2015-06-16
申请号：US13925558
申请日：2013-06-24
发明人： Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
IPC分类号： H01L49/02
CPC分类号： H01L28/10 , H01F17/0006 , H01F27/2804 , H01L21/283 , H01L23/49816 , H01L23/49827 , H01L23/5227 , H01L23/645 , H01L24/16 , H01L2224/0401 , H01L2224/05572 , H01L2224/16225 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
摘要翻译： 根据实施例，半导体器件包括半导体管芯，插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层，第一金属化层包括第一导电图案。 插入器包括第二金属化层，并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 其他实施例考虑了线圈，电感器和/或变压器的其他配置，并考虑了制造方法。
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公开(公告)号：US20140252548A1
公开(公告)日：2014-09-11
申请号：US13791019
申请日：2013-03-08
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Yu , Chin-Wei Kuo , Min-Chie Jeng
CPC分类号： H01L24/11 , H01L24/10 , H01L24/15 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/023 , H01L2224/03 , H01L2224/13147 , H01L2224/81815 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
摘要翻译： 集成电路封装包括管芯。 导电层包括管芯中的再分配层（RDL），或管芯上方的微凸起层，或两者。 微凸起层包括至少一个微凸起线。 滤波器包括导电层。 电容器包括形成在导电层中的电极。
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公开(公告)号：US09960133B2
公开(公告)日：2018-05-01
申请号：US15238520
申请日：2016-08-16
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
CPC分类号： H01L24/11 , H01L24/10 , H01L24/15 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/023 , H01L2224/03 , H01L2224/13147 , H01L2224/81815 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
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公开(公告)号：US09373673B2
公开(公告)日：2016-06-21
申请号：US14719115
申请日：2015-05-21
发明人： Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
IPC分类号： H01L49/02 , H01F17/00 , H01L23/498 , H01L23/522 , H01L23/64 , H01F27/28 , H01L21/283 , H01L23/00
CPC分类号： H01L28/10 , H01F17/0006 , H01F27/2804 , H01L21/283 , H01L23/49816 , H01L23/49827 , H01L23/5227 , H01L23/645 , H01L24/16 , H01L2224/0401 , H01L2224/05572 , H01L2224/16225 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
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公开(公告)号：US09203146B2
公开(公告)日：2015-12-01
申请号：US14173282
申请日：2014-02-05
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01Q1/38 , H01Q1/50 , H01L23/48 , H01L23/66 , H01L25/065 , H01Q1/22 , H01Q9/04 , H01Q9/14 , G06F17/50 , H01L25/07 , H01Q5/357
CPC分类号： H01Q1/50 , G06F17/5068 , H01L23/48 , H01L23/481 , H01L23/66 , H01L25/0657 , H01L25/074 , H01L2223/6616 , H01L2223/6677 , H01L2225/06531 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/1421 , H01L2924/1461 , H01Q1/2283 , H01Q1/38 , H01Q5/357 , H01Q9/0421 , H01Q9/0442 , H01Q9/145 , Y10T29/49016 , H01L2924/00
摘要： An antenna includes a substrate and a conductive top plate over the substrate. A feed line is connected to the top plate, and the feed line comprises a first through-silicon via (TSV) structure passing through the substrate. The feed line is arranged to carry a radio frequency signal. A method of designing an antenna includes selecting a shape of a top plate, determining a size of the top plate based on an intended signal frequency, and determining, based on the shape of the top plate, a location of each TSV of at least one TSV contacting the top plate. A method of implementing an antenna includes forming a first feed line through a substrate, the first feed line comprising a TSV, and forming a top plate over the substrate, the top plate being electrically conductive and connected to the first feed line.
摘要翻译： 天线包括衬底和衬底上的导电顶板。 馈电线连接到顶板，并且馈电线包括穿过衬底的第一穿透硅通孔（TSV）结构。 馈线布置成携带射频信号。 一种设计天线的方法包括：选择顶板的形状，基于预期的信号频率确定顶板的尺寸，并且基于顶板的形状确定每个TSV的位置至少一个 TSV接触顶板。 一种实现天线的方法包括：通过基板形成第一馈电线，第一馈线包括TSV，以及在衬底上形成顶板，顶板是导电的，并连接到第一馈电线。
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公开(公告)号：US10714441B2
公开(公告)日：2020-07-14
申请号：US15946970
申请日：2018-04-06
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
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公开(公告)号：US09449945B2
公开(公告)日：2016-09-20
申请号：US13791019
申请日：2013-03-08
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Yu , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L25/065 , H01L23/00
CPC分类号： H01L24/11 , H01L24/10 , H01L24/15 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/023 , H01L2224/03 , H01L2224/13147 , H01L2224/81815 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
摘要翻译： 集成电路封装包括管芯。 导电层包括管芯中的再分配层（RDL），或管芯上方的微凸起层，或两者。 微凸起层包括至少一个微凸起线。 滤波器包括导电层。 电容器包括形成在导电层中的电极。
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公开(公告)号：US20150255531A1
公开(公告)日：2015-09-10
申请号：US14719115
申请日：2015-05-21
发明人： Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
IPC分类号： H01L49/02 , H01L21/283
CPC分类号： H01L28/10 , H01F17/0006 , H01F27/2804 , H01L21/283 , H01L23/49816 , H01L23/49827 , H01L23/5227 , H01L23/645 , H01L24/16 , H01L2224/0401 , H01L2224/05572 , H01L2224/16225 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
摘要翻译： 根据实施例，半导体器件包括半导体管芯，插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层，第一金属化层包括第一导电图案。 插入器包括第二金属化层，并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 其他实施例考虑了线圈，电感器和/或变压器的其他配置，并考虑了制造方法。
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