公开(公告)号：US20060103017A1

公开(公告)日：2006-05-18

申请号：US11033994

申请日：2005-01-13

申请人： Takamasa Usui ,  Hideki Shibata ,  Tadashi Murofushi ,  Masakazu Jimbo ,  Hiroshi Hirayama

发明人： Takamasa Usui ,  Hideki Shibata ,  Tadashi Murofushi ,  Masakazu Jimbo ,  Hiroshi Hirayama

IPC分类号： H01L23/34

CPC分类号： H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device which comprises a wiring structure capable of reducing stress concentration at a boundary between a wiring and a low dielectric constant insulator even when the low dielectric constant insulator is used as an interlevel or interwiring insulator in a multilevel wiring, suppressing peeling-off of the insulator and having increased heat radiation efficiency is provided by comprising an insulator formed on a semiconductor substrate, a wiring formed in the insulator, and a network dummy formed in the insulator and disposed to be apart from the wiring.

摘要翻译： 即使在多层布线中使用低介电常数绝缘体作为层间或相互连接的绝缘体，也能够抑制布线与低介电常数绝缘体之间的边界处的应力集中的半导体装置，抑制剥离 通过包括形成在半导体衬底上的绝缘体，形成在绝缘体中的布线以及形成在绝缘体中并布置成与布线分开的网络虚拟来提供绝缘体并具有增加的散热效率。

公开(公告)号：US20080203573A1

公开(公告)日：2008-08-28

申请号：US11960209

申请日：2007-12-19

申请人： Takamasa Usui ,  Hideki Shibata ,  Tadashi Murofushi ,  Masakazu Jimbo ,  Hiroshi Hirayama

发明人： Takamasa Usui ,  Hideki Shibata ,  Tadashi Murofushi ,  Masakazu Jimbo ,  Hiroshi Hirayama

IPC分类号： H01L23/48

CPC分类号： H01L23/5222 ,  H01L23/522 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and does not function as a signal line. The conductive pattern is formed in the second wiring layer. The dummy and conductive patterns have an overlapping portion where these patterns overlap each other, and a non-overlapping portion where these patterns overlap each other, as viewed from above the semiconductor substrate.

摘要翻译： 提供了包括第一和第二布线层以及虚拟和导电图案的半导体器件。 第一和第二布线层各自具有中空结构，并且在半导体衬底上彼此垂直地堆叠。 虚设图案形成在第一布线层中，不用作信号线。 导电图案形成在第二布线层中。 伪距和导电图案具有这些图案彼此重叠的重叠部分，以及从半导体基板的上方观察这些图案彼此重叠的非重叠部分。

公开(公告)号：US07750473B2

公开(公告)日：2010-07-06

申请号：US11960209

申请日：2007-12-19

申请人： Takamasa Usui ,  Hideki Shibata ,  Tadashi Murofushi ,  Masakazu Jimbo ,  Hiroshi Hirayama

发明人： Takamasa Usui ,  Hideki Shibata ,  Tadashi Murofushi ,  Masakazu Jimbo ,  Hiroshi Hirayama

IPC分类号： H01L23/48

CPC分类号： H01L23/5222 ,  H01L23/522 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and does not function as a signal line. The conductive pattern is formed in the second wiring layer. The dummy and conductive patterns have an overlapping portion where these patterns overlap each other, and a non-overlapping portion where these patterns overlap each other, as viewed from above the semiconductor substrate.

摘要翻译： 提供了包括第一和第二布线层以及虚拟和导电图案的半导体器件。 第一和第二布线层各自具有中空结构，并且在半导体衬底上彼此垂直地堆叠。 虚设图案形成在第一布线层中，不用作信号线。 导电图案形成在第二布线层中。 伪距和导电图案具有这些图案彼此重叠的重叠部分，以及从半导体基板的上方观察这些图案彼此重叠的非重叠部分。

公开(公告)号：US06946387B2

公开(公告)日：2005-09-20

申请号：US10650974

申请日：2003-08-29

申请人： Junichi Wada ,  Atsuko Sakata ,  Tomio Katata ,  Takamasa Usui ,  Masahiko Hasunuma ,  Hideki Shibata ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura

发明人： Junichi Wada ,  Atsuko Sakata ,  Tomio Katata ,  Takamasa Usui ,  Masahiko Hasunuma ,  Hideki Shibata ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76867 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76889

摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔 和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充 布线槽与Al接线。

公开(公告)号：US07304384B2

公开(公告)日：2007-12-04

申请号：US11063876

申请日：2005-02-24

申请人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.

摘要翻译： 半导体器件包括设置在半导体衬底上并具有形成在其中的开口的层间绝缘膜。 将包含Cu作为主要成分的互连主层嵌入开口部。 隔离膜介于开口内的层间绝缘膜和互连主层之间。 作为主要成分，阻挡膜含有具有层间绝缘膜的成分元素的预定金属元素的化合物。

公开(公告)号：US20070012973A1

公开(公告)日：2007-01-18

申请号：US11418467

申请日：2006-05-05

申请人： Hayato Nasu ,  Takamasa Usui ,  Hideki Shibata

发明人： Hayato Nasu ,  Takamasa Usui ,  Hideki Shibata

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L23/5223 ,  H01L21/76831 ,  H01L21/7687 ,  H01L23/53233 ,  H01L23/53238 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  Y10S257/906 ,  Y10S257/908 ,  Y10S257/924 ,  H01L2924/00

摘要： A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.

摘要翻译： 一种半导体器件包括电容器，该电容器包括至少包括第一绝缘膜的电容器绝缘膜和与第一绝缘膜接触形成的铁电膜，其包含预置金属元素的化合物和第一绝缘膜的构成元素， 主要成分，其介电常数大于第一绝缘膜的介电常数，由Cu中的一种和含有Cu作为主要成分的材料形成的第一电容器电极和形成为在电容器绝缘膜中配合的第二电容器电极 与第一电容器电极。

公开(公告)号：US20070001307A1

公开(公告)日：2007-01-04

申请号：US11440453

申请日：2006-05-25

申请人： Takamasa Usui ,  Hayato Nasu ,  Hideki Shibata

发明人： Takamasa Usui ,  Hayato Nasu ,  Hideki Shibata

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L23/291 ,  H01L23/3178 ,  H01L23/5258 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/564 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/48463 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/45099

摘要： A semiconductor device includes a guard ring formed in an inter-level insulating film on a semiconductor substrate to surround an element forming region on the semiconductor substrate and containing Cu as a main component. And the device further includes a first barrier film formed on an interface between the inter-level insulating film and the guard ring and containing a compound of a preset metal element and a constituent element of the inter-level insulating film as a main component.

摘要翻译： 半导体器件包括形成在半导体衬底上的层间绝缘膜中的保护环，以围绕半导体衬底上的元件形成区域并且以Cu为主要成分。 该装置还包括形成在层间绝缘膜和保护环之间的界面上的第一阻挡膜，并且包含预置金属元素和层间绝缘膜的构成元素的化合物作为主要成分。

公开(公告)号：US07943517B2

公开(公告)日：2011-05-17

申请号：US11877243

申请日：2007-10-23

申请人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.

摘要翻译： 一种制造半导体器件的方法，包括在设置在半导体衬底上的层间绝缘膜中形成开口，形成含有预定金属元素的辅助膜以覆盖开口的内表面，形成主膜以填充开口 在形成辅助膜之后，主膜含有用作互连主层的材料的Cu，并且在形成主膜之前或之后进行热处理，从而扩散辅助膜的预定金属元素 在面向辅助膜的层间绝缘膜的表面上，以在开口内的层间绝缘膜上形成阻挡膜，所述阻挡膜以预定的金属元素与成分元素为主要成分， 的层间绝缘膜。

公开(公告)号：US20050218519A1

公开(公告)日：2005-10-06

申请号：US11063876

申请日：2005-02-24

申请人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.

摘要翻译： 半导体器件包括设置在半导体衬底上并具有形成在其中的开口的层间绝缘膜。 将包含Cu作为主要成分的互连主层嵌入开口部。 隔离膜介于开口内的层间绝缘膜和互连主层之间。 作为主要成分，阻挡膜含有具有层间绝缘膜的成分元素的预定金属元素的化合物。

公开(公告)号：US06673704B2

公开(公告)日：2004-01-06

申请号：US10189598

申请日：2002-07-08

申请人： Junichi Wada ,  Atsuko Sakata ,  Tomio Katata ,  Takamasa Usui ,  Masahiko Hasunuma ,  Hideki Shibata ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura

发明人： Junichi Wada ,  Atsuko Sakata ,  Tomio Katata ,  Takamasa Usui ,  Masahiko Hasunuma ,  Hideki Shibata ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura

IPC分类号： H01L2140

CPC分类号： H01L21/76867 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76889

摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔 和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充 布线槽与Al接线。