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    XOR CMOS logic gate
    4.
    发明授权
    XOR CMOS logic gate 失效
    异或CMOS逻辑门

    公开(公告)号：US5576637A

    公开(公告)日：1996-11-19

    申请号：US441460

    申请日：1995-05-15

    申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

    IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21

    CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

    摘要： An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input. The gates of the second and fourth nMIS transistors and the second and fourth pMIS transistors are connected to one another and provided with a second input. The sources of the second and third nMIS transistors are connected to each other and provide the exclusive OR of the first and second inputs.

    摘要翻译： 异或电路包括第一串联电路，其中第一pMIS晶体管的源极连接到正电压电源线。 第一pMIS晶体管的漏极经由第二nMIS晶体管连接到第一nMIS晶体管的漏极。 第一nMIS晶体管的源极经由第四nMIS晶体管连接到低压电源线。 第二串联电路具有通过第二pMIS晶体管连接到高压电源线的第三nMIS晶体管的漏极。 第三个nMIS晶体管的源极连接到第三个pMIS晶体管的源极。 第三个pMIS晶体管的漏极通过第四个pMIS晶体管连接到低压电源线。 第一和第三nMIS晶体管和第一和第三pMIS晶体管的栅极彼此连接并提供有第一输入。 第二和第四nMIS晶体管和第二和第四pMIS晶体管的栅极彼此连接并提供有第二输入。 第二和第三nMIS晶体管的源极彼此连接并提供第一和第二输入的异或。

    Nonvolatile semiconductor memory
    8.
    发明授权
    Nonvolatile semiconductor memory 失效

    公开(公告)号：US5590074A

    公开(公告)日：1996-12-31

    申请号：US466732

    申请日：1995-06-06

    申请人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C29/04 ,  G11C11/34

    CPC分类号： G11C16/30 ,  G11C16/26 ,  G11C29/04 ,  G06F2201/81

    摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

    Nonvolatile semiconductor memory with pre-read means
    9.
    发明授权
    Nonvolatile semiconductor memory with pre-read means 失效
    具有预读功能的非易失性半导体存储器

    公开(公告)号：US5572463A

    公开(公告)日：1996-11-05

    申请号：US416281

    申请日：1995-04-04

    申请人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C16/30 ,  G11C16/26 ,  G11C29/04 ,  G06F2201/81

    摘要： A semiconductor memory having address buffer means, memory cell means, word line selection means, bit line selection means, an output buffer, first address generation means connected to the address buffer means, for providing and address for specifying a group of data pieces, and second address generation means for providing addresses for specifying the data pieces, respectively, the semiconductor memory comprising first reading means for selecting and reading a group of data pieces through one of the word line selection means and bit line selection means according to an address provided by the first address generation means, second reading means for selecting the data pieces, which have been selected and read according to the address provided by the first address generation means, through one of the bit line selection means and word line selection means according addresses provided by the second address generation means and providing them to the output buffer; and pre-reading means for reading another group of data pieces according the another address to be provided by the first address generation means while the preceding data pieces are being read according to the preceding address provided by the first address generation means and being selectively provided to the output buffer according to the addresses provided by the second address generation means.

    摘要翻译： 具有地址缓冲器装置，存储单元装置，字线选择装置，位线选择装置，输出缓冲器，连接到地址缓冲器装置的第一地址产生装置的半导体存储器，用于提供和寻址用于指定一组数据片段，以及 第二地址产生装置，分别提供用于指定数据片段的地址，所述半导体存储器包括第一读取装置，用于根据由字线选择装置和位线选择装置中的一个选择和读取一组数据片段， 第一地址产生装置，用于根据由第一地址产生装置提供的地址选择和读取的数据片段的第二地址产生装置，通过位线选择装置和字线选择装置之一，根据由 第二地址产生装置并将其提供给输出缓冲器; 以及预读取装置，用于根据由第一地址产生装置提供的另一地址读取另一组数据片段，同时根据由第一地址产生装置提供的先前地址读取先前的数据，并且选择性地提供给 所述输出缓冲器根据由所述第二地址产生装置提供的地址。

    Nonvolatile semiconductor memory
    10.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US5490107A

    公开(公告)日：1996-02-06

    申请号：US996942

    申请日：1992-12-28

    申请人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    发明人： Takao Akaogi ,  Masanobu Yoshida ,  Yasushige Ogawa ,  Yasushi Kasa ,  Shouichi Kawamura

    IPC分类号： G11C16/26 ,  G11C16/30 ,  G11C29/04 ,  G11C11/34

    CPC分类号： G11C16/30 ,  G11C16/26 ,  G11C29/04 ,  G06F2201/81

    摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (V.sub.CC), the gate of the transistor being connected to a low source voltage (V.sub.ss) to provide an internal source voltage (V.sub.ci), a combination of an arrangement for dropping the external source voltage (V.sub.cc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (V.sub.pp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (V.sub.ref) as a lower threshold (V.sub.th) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (V.sub.ref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

    摘要翻译： 非易失性半导体存储器采用读出放大器，用于提供稳定的源极电压的电路和用于实现高速和可靠的读取和写入操作的电路。 半导体存储器具有非易失性可擦除存储单元晶体管的矩阵。 半导体存储器采用有效地使用多个源极电压并施加验证电压以读取放大器和字线的布置，用于检测读出放大器的输出的写入验证装置，用于将读出放大器的输出与 用于确定存储单元晶体管的写入状态是否可接受的参考值，用于响应于流向存储单元晶体管的电流，利用反相器和晶体管调整读出放大器的输出的装置，以改善 感测放大器的驱动速度，使用连接到外部源电压（VCC）的n沟道耗尽晶体管的内部源极电压产生装置，晶体管的栅极连接到低源电压（Vss）以提供内部源极 电压（Vci），用于将用于读取的外部源电压（Vcc）下降到预定值的装置的组合 驱动存储器中的读取电路和用于丢弃用于写入的外部电压（Vpp）的布置，以产生用于写入后验证操作的字线电位，用于将参考电压（Vref）设置为 允许单元晶体管（1100〜1122）的下限阈值（Vth），并将数据总线（13）的电压与参考电压（Vref）进行比较，以对所有存储单元晶体管同时执行擦除验证操作，以及 用于在读出放大器的读取时间期间访问下一个地址的预读布置，以提高读取速度。