公开(公告)号：US20090201717A1

公开(公告)日：2009-08-13

申请号：US12366396

申请日：2009-02-05

申请人： Takashi MAEDA ,  Yoshihiro UEDA ,  Kenji TSUCHIDA

发明人： Takashi MAEDA ,  Yoshihiro UEDA ,  Kenji TSUCHIDA

IPC分类号： G11C11/00 ,  G11C11/416

CPC分类号： G11C11/1653 ,  G11C11/1673 ,  G11C11/1675

摘要： A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines, a first memory element which has one and the other terminals connected to the first and third bit lines, and changes to one of first and second resistance states, a first reference element having one and the other terminals connected to the fourth and sixth bit lines, and set in the first resistance state, a second reference element having one and the other terminals connected to the fifth and sixth bit lines, and set in the second resistance state, and a sense amplifier having first and second input terminals connected to the first and fourth bit lines.

摘要翻译： 电阻变化存储器包括沿相同方向运行的第一和第二位线，与第一和第二位线并行运行的第三位线，沿相同方向运行的第四和第五位线，平行于第一位线的第六位线 第四和第五位线，第一存储器元件，其具有连接到第一和第三位线的一个端子和另一个端子，并且改变为第一和第二电阻状态中的一个;第一参考元件，其中一个和另一个端子连接到 第四和第六位线，并且设置在第一电阻状态，第二参考元件，其中一个和另一个端子连接到第五和第六位线，并被设置在第二电阻状态，以及读出放大器，具有第一和第二输入 连接到第一和第四位线的端子。

公开(公告)号：US20100046274A1

公开(公告)日：2010-02-25

申请号：US12543793

申请日：2009-08-19

申请人： Kenji TSUCHIDA ,  Yoshihiro UEDA

发明人： Kenji TSUCHIDA ,  Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

摘要： A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.

摘要翻译： 电阻变化存储器包括两个存储单元阵列，每个存储单元阵列包括多个存储单元，存储单元包括可变电阻元件，分别提供给两个存储单元阵列的两个参考单元阵列，每个参考单元阵列包括多个参考单元， 所述参考单元具有参考值，以及由所述两个存储单元阵列共享的读出放大器，并且通过使用与包括所述存储单元阵列的第一存储单元阵列不同的第二存储单元阵列对应的参考单元阵列来检测所访问的存储器单元中的数据 存取存储单元 在读取数据时，一个参考单元阵列中的特定参考单元总是基于一个存储单元阵列作为单元而被激活用于地址空间。

公开(公告)号：US20070279963A1

公开(公告)日：2007-12-06

申请号：US11673206

申请日：2007-02-09

申请人： Kenji TSUCHIDA ,  Yoshihiro UEDA

发明人： Kenji TSUCHIDA ,  Yoshihiro UEDA

IPC分类号： G11C11/00

CPC分类号： G11C11/1657 ,  G11C11/1655

摘要： The first memory cell in even columns is composed of a first resistance change element one end of which is connected to a first bit line, and first and second FETs connected in parallel between the other end of the first resistance change element and a second bit line. The second memory cell in odd columns is composed of a second resistance change element one end of which is connected to a third bit line, and third and fourth FETs connected in parallel between the other end of the second resistance change element and a fourth bit line. A gate of the first FET is connected to the first word line. Gates of the second and third FETs are connected together to the second word line. A gate of the fourth FET is connected to the third word line.

摘要翻译： 偶数列中的第一存储单元由第一电阻变化元件组成，其一端连接到第一位线，并且第一和第二FET并联连接在第一电阻变化元件的另一端和第二位线 。 奇数列中的第二存储单元由第二电阻变化元件组成，其一端连接到第三位线，第三和第四FET并联连接在第二电阻变化元件的另一端和第四位线之间 。 第一个FET的栅极连接到第一个字线。 第二和第三FET的栅极连接在一起到第二字线。 第四FET的栅极连接到第三字线。

公开(公告)号：US20100165701A1

公开(公告)日：2010-07-01

申请号：US12536341

申请日：2009-08-05

申请人： Yoshihiro UEDA ,  Kenji TSUCHIDA ,  Kiyotaro ITAGAKI

发明人： Yoshihiro UEDA ,  Kenji TSUCHIDA ,  Kiyotaro ITAGAKI

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C7/10

CPC分类号： G11C13/00 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C2013/0054 ,  G11C2213/79

摘要： A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier.

摘要翻译： 电阻存储器包括多个存储单元，具有相互不同的电阻值的多个参考单元，至少一个读出放大器，其具有连接到从多个存储单元中选择的一个选定存储单元的第一输入端， 读取，以及连接到在读取时从多个参考单元中选择的一个选择的参考单元的第二输入端子，以及保持所述至少一个读出放大器的偏移信息的一个锁存电路。 电阻存储器还包括解码器，其根据偏移信息从多个参考单元中选择一个选定的参考单元，并将所选择的一个参考单元连接到至少一个读出放大器的第二输入端。

公开(公告)号：US20090086532A1

公开(公告)日：2009-04-02

申请号：US12243350

申请日：2008-10-01

申请人： Kenji TSUCHIDA

发明人： Kenji TSUCHIDA

IPC分类号： G11C11/02 ,  G11C11/14 ,  G11C7/14

CPC分类号： G11C5/147 ,  G11C11/1673 ,  G11C11/1697

摘要： A magnetic random access memory includes a memory cell having a first magnetoresistive effect element, a reference cell having a second magnetoresistive effect element set in a low-resistance state, a first bit line connected to the memory cell, and set at a first bias potential in a read operation, a second bit line connected to the reference cell, and set at a second bias potential in the read operation, and a reference voltage generator including a reference current generator having a third magnetoresistive effect element set in the high-resistance state, and a current-voltage converter having a fourth magnetoresistive effect element set in the low-resistance state, the reference current generator generating a first electric current by applying the first bias potential to the third magnetoresistive effect element, and the current-voltage converter generating the second bias potential by supplying a second electric current to the fourth magnetoresistive effect element.

摘要翻译： 磁性随机存取存储器包括具有第一磁阻效应元件的存储单元，具有设置在低电阻状态的第二磁阻效应元件的参考单元，连接到存储单元的第一位线，并且被设置为第一偏置电位 在读取操作中，连接到参考单元的第二位线并且在读取操作中被设置为第二偏置电位;以及参考电压发生器，其包括具有设置在高电阻状态的第三磁阻效应元件的参考电流发生器 以及具有设置在低电阻状态的第四磁阻效应元件的电流 - 电压转换器，所述参考电流发生器通过向所述第三磁阻效应元件施加所述第一偏置电位而产生第一电流，并且所述电流 - 电压转换器产生 所述第二偏置电位通过向所述第四磁阻效应元件提供第二电流。

公开(公告)号：US20150228320A1

公开(公告)日：2015-08-13

申请号：US14692239

申请日：2015-04-21

申请人： Yutaka SHIRAI ,  Naoki SHIMIZU ,  Kenji TSUCHIDA ,  Yoji WATANABE ,  Ji Hyae BAE ,  Yong Ho KIM

发明人： Yutaka SHIRAI ,  Naoki SHIMIZU ,  Kenji TSUCHIDA ,  Yoji WATANABE ,  Ji Hyae BAE ,  Yong Ho KIM

IPC分类号： G11C8/18 ,  G11C8/10

CPC分类号： G11C7/12 ,  G11C7/1039 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

摘要翻译： 根据一个实施例，存储器包括具有存储体的存储单元阵列，每个存储体包括行，对应于行的第一字线，锁存第一行地址信号的地址锁存电路， 第一字线，以及控制电路，被配置为当加载第一命令时，基于存储体地址信号执行第一操作，该第一操作激活存储区中的一个存储体;以及第二操作，其将第一行地址信号锁存在地址中 并且执行第三操作，当在第一命令之后加载第二命令时，基于第二行地址信号和锁存在地址锁存电路中的第一行地址信号，由行解码器激活第一字线之一。

公开(公告)号：US20140286115A1

公开(公告)日：2014-09-25

申请号：US14020534

申请日：2013-09-06

申请人： Yutaka SHIRAI ,  Naoki SHIMIZU ,  Kenji TSUCHIDA ,  Yoji WATANABE ,  Ji Hyae BAE ,  Yong Ho KIM

发明人： Yutaka SHIRAI ,  Naoki SHIMIZU ,  Kenji TSUCHIDA ,  Yoji WATANABE ,  Ji Hyae BAE ,  Yong Ho KIM

IPC分类号： G11C7/12 ,  G11C8/10 ,  G11C8/12

CPC分类号： G11C7/12 ,  G11C7/1039 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

摘要翻译： 根据一个实施例，存储器包括具有存储体的存储单元阵列，每个存储体包括行，对应于行的第一字线，锁存第一行地址信号的地址锁存电路， 第一字线，以及控制电路，被配置为当加载第一命令时，基于存储体地址信号执行第一操作，该第一操作激活存储区中的一个存储体;以及第二操作，其将第一行地址信号锁存在地址中 并且执行第三操作，当在第一命令之后加载第二命令时，基于第二行地址信号和锁存在地址锁存电路中的第一行地址信号，由行解码器激活第一字线之一。

公开(公告)号：US20100238707A1

公开(公告)日：2010-09-23

申请号：US12715231

申请日：2010-03-01

申请人： Kenji TSUCHIDA

发明人： Kenji TSUCHIDA

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： H01L27/24 ,  G11C8/08 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/228

摘要： A resistance change memory device includes memory cells including two transistors connected in parallel between a first node and a connecting node and a variable resistance element whose one end is connected to the connecting node. The first node of each memory cell and a second node, which is the other end of the variable resistance element of the memory cell, are connected to different bit lines. The first node of a one memory cell and the first node of another memory cell which is adjacent on a first side along the second axis to the one memory are connected to the same bit line. The second node of the one memory cell and the second node of still another memory cell which is adjacent on a second side along the second axis to the one memory cell are connected to the same bit line.

摘要翻译： 电阻变化存储器件包括：存储单元，包括并联连接在第一节点和连接节点之间的两个晶体管，以及可变电阻元件，其一端连接到连接节点。 每个存储单元的第一节点和作为存储单元的可变电阻元件的另一端的第二节点连接到不同的位线。 一个存储单元的第一个节点和另一个存储单元的第一个节点连接到相同的位线，该存储单元的第一个边沿第二个轴与第一个轴相邻。 一个存储单元的第二个节点和另一个存储单元的另一个存储单元的第二个节点连接到相同的位线。