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    Ferroelectric memory and non-volatile memory cell for same
    2.
    发明授权
    Ferroelectric memory and non-volatile memory cell for same 失效
    铁电存储器和非易失性存储器单元相同

    公开(公告)号：US5541870A

    公开(公告)日：1996-07-30

    申请号：US330989

    申请日：1994-10-28

    申请人： Takashi Mihara ,  Hitoshi Watanabe ,  Hiroyuki Yoshimori ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    发明人： Takashi Mihara ,  Hitoshi Watanabe ,  Hiroyuki Yoshimori ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    IPC分类号： G11C17/00 ,  G11C11/22 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11502 ,  G11C11/22

    摘要： A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.

    摘要翻译： 一种非易失性集成电路存储器，其中存储单元包括覆盖第一沟道区的第一晶体管栅极，覆盖第二沟道区的铁电材料和覆盖第三沟道区的第二晶体管栅极。 通道区域串联连接，优选地是单个半导体通道的连续部分。 固体通道连接到铁电体的矫顽电压的20％至50％的板电压。 读出放大器通过位线连接到第三通道区域。 读出逻辑“1”状态之后的位线的上升通过在读出放大器上升之前切断第三通道来防止铁电材料的干扰。

    Method and apparatus for reduced fatigue in ferroelectric memory elements
    8.
    发明授权
    Method and apparatus for reduced fatigue in ferroelectric memory elements 失效
    铁电存储元件疲劳减少的方法和装置

    公开(公告)号：US5487032A

    公开(公告)日：1996-01-23

    申请号：US338003

    申请日：1994-11-10

    申请人： Takashi Mihara ,  Hitoshi Watanabe ,  Hiroyuki Yoshimori ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    发明人： Takashi Mihara ,  Hitoshi Watanabe ,  Hiroyuki Yoshimori ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： A method and apparatus for programming ferroelectric memory cells which reduces fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors and transistors. Alteration of the rise AC fall times associated with signals used to switch ferroelectric device polarization are shown to reduce fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Slowing the rise and fall times as well as the rate of signal level rise and fall, (signal shape), are shown to reduce the fatigue effects of switching polarization of ferroelectric devices. Methods and apparatus for producing a triangular ("sawtooth") signal waveform, a Gaussian signal waveform, and a waveform having exponential rise and fall times are disclosed.

    摘要翻译： 一种用于编程铁电存储器单元的方法和装置，其减少与诸如铁电电容器和晶体管之类的存储单元相关联的铁电体器件的开关极化的疲劳效应。 示出了与用于切换铁电体器件极化的信号相关联的上升AC下降时间的变化，以减少铁电材料的疲劳，从而增加铁电存储器单元的使用寿命。 降低上升和下降时间以及信号电平上升和下降（信号形状）的速率，可以减少铁电元件开关极化的疲劳效应。 公开了用于产生三角形（“锯齿”）信号波形，高斯信号波形和具有指数上升和下降时间的波形的方法和装置。

    Ferroelectric non-volatile memory unit
    9.
    发明授权
    Ferroelectric non-volatile memory unit 失效
    铁电非易失性存储单元

    公开(公告)号：US5523964A

    公开(公告)日：1996-06-04

    申请号：US224241

    申请日：1994-04-07

    申请人： Larry D. McMillan ,  Takashi Mihara ,  Hiroyuki Yoshimori ,  John W. Gregory ,  Carlos A. Paz de Araujo

    发明人： Larry D. McMillan ,  Takashi Mihara ,  Hiroyuki Yoshimori ,  John W. Gregory ,  Carlos A. Paz de Araujo

    IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C11/22 ,  G11C11/223

    摘要： An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant .epsilon.f and the gate insulator has a dielectric constant .epsilon.g. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate. The memory unit has the parametric relationships: Cf

    摘要翻译： 集成电路非易失性非破坏性读出存储单元包括具有第一和第二电极的铁电电容器，电容Cf和区域Af，以及具有形成栅极电容器的栅极，源极和漏极的晶体管 具有面积Ag和栅极电容Cg，栅极重叠b和沟道深度a，其中电容器第一电极连接到晶体管的栅极。 铁电材料具有介电常数εf，栅极绝缘体具有介电常数εg。 恒定参考电压的源可连接到第一电极。 位线连接到第二电极。 在一个实施例中，第一电极和栅极是相同的导电构件。 在另一个实施例中，第二电极和栅极是相同的导电构件，并且第一电极由晶体管源的延伸和栅极下方的漏极形成，铁电材料在源极和漏极延伸部分之间以及栅极之间。 存储器单元具有参数关系：Cf <5xCg，Af / = 2a和epsilon g> / = epsilon f / 8。