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公开(公告)号：US08487364B2
公开(公告)日：2013-07-16
申请号：US12792378
申请日：2010-06-02
IPC分类号： H01L29/792 , H01L21/3205 , H01L21/4763
摘要： A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.
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2.发明授权公开(公告)号：US08598649B2
公开(公告)日：2013-12-03
申请号：US12792378
申请日：2010-06-02
IPC分类号： H01L29/792 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11565 , H01L21/28282 , H01L27/11568
摘要： A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：半导体衬底，其具有被分隔成沿第一方向延伸的多个半导体部分的上部; 设置在半导体部分上的电荷存储膜; 字线电极，其设置在所述半导体基板上并沿与所述第一方向交叉的第二方向延伸; 以及一对选择栅电极，其设置在所述半导体基板上的所述字线电极的所述第一方向的两侧，并且沿所述第二方向延伸，所述半导体部分的每个的角部与所述选择中的每一个之间的最短距离 栅电极比与半导体部分的角部和字线电极之间的平行于第二方向的截面中的最短距离更长。
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3.发明授权公开(公告)号：US08837223B2
公开(公告)日：2014-09-16
申请号：US13600991
申请日：2012-08-31
申请人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
发明人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L21/28273 , H01L27/11524 , H01L27/11531 , H01L29/788
摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：其中布置多个NAND单元单元的存储单元阵列，包括多个存储单元的NAND单元单元和选择栅极晶体管，所述存储单元包括半导体层， 栅极绝缘膜，电荷蓄积层和控制栅极; 和控制电路。 控制电路根据写入数据将每个存储器单元的写入条件调整到与要写入的数据内的存储单元相邻的存储单元和存储单元。
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4.发明申请公开(公告)号：US20130235666A1
公开(公告)日：2013-09-12
申请号：US13600991
申请日：2012-08-31
申请人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
发明人： Wataru Sakamoto , Fumitaka Arai , Takashi Kobayashi , Ken Komiya , Shinichi Sotome , Tatsuya Kato
IPC分类号： G11C16/04 , H01L29/788 , H01L21/28
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L21/28273 , H01L27/11524 , H01L27/11531 , H01L29/788
摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：其中布置多个NAND单元单元的存储单元阵列，包括多个存储单元的NAND单元单元和选择栅极晶体管，所述存储单元包括半导体层， 栅极绝缘膜，电荷蓄积层和控制栅极; 和控制电路。 控制电路根据写入数据将每个存储器单元的写入条件调整到与要写入的数据内的存储单元相邻的存储单元和存储单元。
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公开(公告)号：US08212303B2
公开(公告)日：2012-07-03
申请号：US12821689
申请日：2010-06-23
申请人： Wataru Sakamoto
发明人： Wataru Sakamoto
IPC分类号： H01L29/94
CPC分类号： H01L29/42324 , G11C16/0466 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L27/11529 , H01L27/11548 , H01L27/11575 , H01L29/4234
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate including a first region in which a memory cell transistor is arranged, a second region in which an electrode that extracts a word line electrically connected to the memory cell transistor is arranged, and a third region in which a peripheral transistor is arranged, the semiconductor substrate including an element isolation layer which separates adjacent active regions, first active regions provided in the first region and each having a first width, second active regions provided in the second region and each having a second width greater than the first width, third active regions provided in the third region and each having a third with greater than the first width. An upper surface of an element isolation layer in the second region is higher than that of an element isolation layer in the first region.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：半导体衬底，包括其中布置有存储单元晶体管的第一区域;第二区域，其中布置提取与存储单元晶体管电连接的字线的电极;以及 其中配置有外围晶体管的第三区域，所述半导体衬底包括分隔相邻有源区的元件隔离层，设置在所述第一区域中的每一个具有第一宽度的第一有源区，并且每个具有第一宽度，所述第二有源区设置在所述第二区中， 具有大于第一宽度的第二宽度，设置在第三区域中的每一个具有大于第一宽度的第三有效区域。 第二区域中的元件隔离层的上表面高于第一区域中的元件隔离层的上表面。
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公开(公告)号：US20100194343A1
公开(公告)日：2010-08-05
申请号：US12699593
申请日：2010-02-03
IPC分类号： H02J7/00
CPC分类号： H02J7/0016 , H02J7/0021 , H02J7/0026
摘要： Provided are a battery state monitoring circuit and a battery device which are capable of inhibiting discharge without enabling an overdischarge cell balance function when an overcurrent detection circuit detects a discharge overcurrent, without the need for an additional terminal of the battery state monitoring circuit. A detection signal of the overcurrent detection circuit is input to each of a communication terminal for overdischarge signal and a communication terminal for overcharge signal included in the battery state monitoring circuit provided on a side of the overcurrent detection circuit. An overdischarge cell balance circuit outputs a cell balance signal when an overdischarge detection signal indicates an overdischarge non-detected state, an overdischarge signal indicates an overdischarge detected state, and an overcharge signal indicates an overcharge non-detected state.
摘要翻译： 提供一种电池状态监视电路和电池装置，其能够在过电流检测电路检测到放电过电流时能够抑制放电，而不需要过放电电池平衡功能，而不需要电池状态监视电路的附加端子。 过电流检测电路的检测信号输入到过放电信号的通信端子和设置在过电流检测电路一侧的电池状态监视电路中的过充电信号的通信端子。 当过放电检测信号表示过放电未检测状态，过放电信号表示过放电检测状态，过充电单元平衡电路输出单元平衡信号，过充电信号表示过充电未检测状态。
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7.发明申请MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE USING INSULATING FILM AS CHARGE STORAGE LAYER 有权使用绝缘膜作为充电储存层的半导体存储器件的制造方法公开(公告)号：US20090053885A1
公开(公告)日：2009-02-26
申请号：US12194050
申请日：2008-08-19
申请人： Wataru Sakamoto , Mitsuhiro Noguchi
发明人： Wataru Sakamoto , Mitsuhiro Noguchi
IPC分类号： H01L21/3205
CPC分类号： H01L21/31133 , H01L21/28282 , H01L21/823425 , H01L21/823468 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor memory device includes forming a first gate electrode having a charge storage layer, a block layer, and a control gate electrode on a first region of a semiconductor substrate, forming a second gate electrode on a second region of the semiconductor substrate, forming a protective insulating film on a side surface of the block layer, exposing the first region while covering the second region on the semiconductor substrate with a photoresist, using the photoresist, the first gate electrode, and the protective insulating film as masks to implant an impurity into the first region of the semiconductor substrate, and removing the photoresist by wet etching which uses a mixed solution containing H2SO4 and H2O2. The protective insulating film having an etching selective ratio of 1:100 or above with respect to the photoresist under wet etching conditions using the mixed solution.
摘要翻译： 半导体存储器件的制造方法包括在半导体衬底的第一区域上形成具有电荷存储层的第一栅电极，阻挡层和控制栅电极，在半导体衬底的第二区域上形成第二栅电极 衬底，在阻挡层的侧表面上形成保护绝缘膜，使用光致抗蚀剂，第一栅极电极和保护绝缘膜作为掩模，用光致抗蚀剂暴露第一区域同时覆盖半导体衬底上的第二区域， 将杂质注入半导体衬底的第一区域，并通过使用含有H 2 SO 4和H 2 O 2的混合溶液的湿法蚀刻去除光致抗蚀剂。 该保护绝缘膜在湿蚀刻条件下使用混合溶液相对于光致抗蚀剂的蚀刻选择比为1:100或更高。
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公开(公告)号：US6120750A
公开(公告)日：2000-09-19
申请号：US273275
申请日：1999-03-22
CPC分类号： C01G25/006 , C01P2002/34
摘要： A lead-containing complex oxide containing substantially no alkali metal is produced under hydrothermal conditions in the absence of alkali metals using a Pb source which serves also as a mineralizer for precipitating the lead-containing complex oxide. Preferred Pb source acting as the mineralizer is lead oxide.
摘要翻译： 在不存在碱金属的水热条件下，使用也用作沉淀含铅复合氧化物的矿化剂的Pb源产生基本上不含碱金属的含铅复合氧化物。 作为矿化剂的优选Pb源是氧化铅。
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公开(公告)号：US5374923A
公开(公告)日：1994-12-20
申请号：US945783
申请日：1992-09-16
申请人： Wataru Sakamoto
发明人： Wataru Sakamoto
IPC分类号： G06F1/26 , G01R19/155 , G11C11/401 , H01L21/822 , H01L27/04 , H02J1/00 , H03K17/22 , G08B21/00
CPC分类号： G01R19/155
摘要： A power-on detecting circuit includes a capacitance for sensing power-on, and a signal generating circuit which responds to the output node potential of capacitance by generating a signal indicative of the power-on. The signal generating circuit includes inverter circuits forming a latch circuit. The power-on detecting circuit includes a control circuit, which adjusts driving capabilities of inverter circuits at the power-on and power-off, or an activation control circuit, which delays the activation timing. The control circuit differentiates the driving capability of the latch circuit formed of inverter circuits at the power-on from that at the power-off. Activation control circuit activates signal generating circuit at the time the potential of the output node ND10 of a sensing circuit rises above the potential of the output node of signal generating circuit.
摘要翻译： 上电检测电路包括用于感测上电的电容，以及信号发生电路，其通过产生表示通电的信号来响应电容的输出节点电位。 信号发生电路包括形成锁存电路的反相器电路。 上电检测电路包括控制电路，其调节上电和断电时的逆变器电路的驱动能力，或启动控制电路，其延迟激活定时。 控制电路将上电时由逆变器电路构成的锁存电路的驱动能力与断电时的驱动能力区分开。 激活控制电路在感测电路的输出节点ND10的电位上升到信号发生电路的输出节点的电位以上时激活信号发生电路。
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公开(公告)号：US20210188586A1
公开(公告)日：2021-06-24
申请号：US16722474
申请日：2019-12-20
IPC分类号： B65H20/02 , B41J11/00 , B65H20/10 , B65H23/192 , B41J11/04
摘要： Systems and methods for dryer rollers of a print system with increasing wrap angles. In one embodiment a dryer includes a turning device configured to rotate about an axis, and to guide a web of print media. The dryer also includes rollers configured to transport the web from an entrance of the dryer to the turning device. The rollers include a series of three or more rollers positioned in the dryer to consecutively increase an amount of contact area with the web as the web travels toward the turning device.
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