公开(公告)号：US4803375A

公开(公告)日：1989-02-07

申请号：US941192

申请日：1986-12-12

申请人： Tamio Saito ,  Satoshi Takayama ,  Yoshiyuki Suda ,  Osamu Shimada ,  Ken-ichi Mori

发明人： Tamio Saito ,  Satoshi Takayama ,  Yoshiyuki Suda ,  Osamu Shimada ,  Ken-ichi Mori

IPC分类号： H01L27/144 ,  H01L27/146 ,  H01J40/14 ,  H01L27/14

CPC分类号： H01L27/14665 ,  H01L27/1446

摘要： An image sensor, comprising a semiconductor layer formed on at least a first region of a substrate; first electrodes arranged in line and electrically connected to the semiconductor layer of said first region; and second electrodes arranged in line and electrically connected to said semiconductor layer of said first region. The second electrodes are respectively formed as a common electrode, and each of the first electrodes, a portion of said second electrode facing the first electrode and the semiconductor layer positioned therebetween form a photo-sensing element. First wires respectively extend from said first electrodes to a second region of said substrate. An insulating layer is continuously formed on the first and second regions, covering said photo-sensing elements and the first wires as well as second wires formed in parallel on the insulating layer of said second region. The second wires are electrically connected to the first wires at through holes formed in the insulating layer.

摘要翻译： 一种图像传感器，包括形成在基板的至少第一区域上的半导体层; 排列成直线并与所述第一区域的半导体层电连接的第一电极; 以及与所述第一区域的所述半导体层电连接并且电连接的第二电极。 第二电极分别形成为公共电极，并且每个第一电极，所述第二电极的面向第一电极的部分和位于其间的半导体层形成光敏元件。 第一导线分别从所述第一电极延伸到所述衬底的第二区域。 在第一和第二区域上连续地形成绝缘层，覆盖所述光敏元件和第一布线以及平行地形成在所述第二区域的绝缘层上的第二布线。 第二导线在形成在绝缘层中的通孔处电连接到第一布线。

公开(公告)号：US4755859A

公开(公告)日：1988-07-05

申请号：US911440

申请日：1986-09-25

申请人： Yoshiyuki Suda ,  Satoshi Takayama

发明人： Yoshiyuki Suda ,  Satoshi Takayama

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L29/06 ,  H01L29/34 ,  H01L29/80

CPC分类号： H01L29/7722

摘要： A thin film static induction transistor comprises a first n type semiconductor layer provided on an insulative substrate and a second n type semiconductor layer mounted on the first layer. The second layer includes a first region having a first level top wall and a second region having a second level top wall lower that the first level top wall. The first and second regions are alternately arranged. A third semiconductor layer is provided on the first level top wall. A recess is formed which includes side walls of the third layers, side wall of the first regions and the second level top wall. A fourth semiconductor layer is deposited on the inner wall of the recess, and a gate electrode is provided on the fourth layer. The fourth layer consists of an intrinsic semiconductor layer or a semiconductor layer having a lower impurity concentration than the second layer.

摘要翻译： 薄膜静电感应晶体管包括设置在绝缘基板上的第一n型半导体层和安装在第一层上的第二n型半导体层。 第二层包括具有第一层顶壁的第一区域和具有第一层顶壁的第二层顶壁的第二区域。 第一区域和第二区域交替布置。 在第一级顶壁上设置第三半导体层。 形成包括第三层的侧壁，第一区域的侧壁和第二水平顶壁的凹部。 第四半导体层沉积在凹槽的内壁上，栅电极设置在第四层上。 第四层由本征半导体层或具有比第二层低的杂质浓度的半导体层组成。

公开(公告)号：US20100308341A1

公开(公告)日：2010-12-09

申请号：US12745133

申请日：2008-09-08

申请人： Yoshiyuki Suda ,  Yutaka Ota

发明人： Yoshiyuki Suda ,  Yutaka Ota

IPC分类号： H01L29/24

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L21/8213 ,  H01L27/1021 ,  H01L27/1022 ,  H01L27/24

摘要： A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.

摘要翻译： 实现高集成度以及减少读出时间的开关电阻RAM。 形成由N阱11构成的集电极构成的NPN型双极晶体管BT，在N阱11的表面形成的由P +型Si层12A构成的基极层和由N阱11的表面形成的发射极层 形成在P +型Si层12A的表面上的N +型Si层15。 而且，形成与N +型Si层15电连接的字线WL0，与字线WL0相交的位线BL1〜BL4。 此外，形成在P +型Si层12A的表面上形成的多个开关层14，其各自与对应的每个位线电连接，并且在导通状态和断开状态之间切换以及电位固定线 19A以将P +型Si层12A固定在预定电位。

公开(公告)号：US4510412A

公开(公告)日：1985-04-09

申请号：US528841

申请日：1983-09-02

申请人： Yoshiyuki Suda ,  Katsunori Yokoyama ,  Chiaki Tanuma

发明人： Yoshiyuki Suda ,  Katsunori Yokoyama ,  Chiaki Tanuma

IPC分类号： G12B1/00 ,  H01L41/083 ,  H01L41/09 ,  H02N2/00 ,  H02N2/04 ,  H01L41/08

CPC分类号： H02N2/02 ,  G12B1/00 ,  H01L41/0833

摘要： A piezoelectric displacing device includes a plurality of longitudinal effect-type piezoelectric displacing members arranged juxtaposed to each other such that displacement axes thereof are substantially parallel to each other, each of said piezoelectric displacing member converting a voltage applied thereto to a mechanical displacement. Connectors are provided which mechanically connect the piezoelectric displacing members in series with each other and derive a sum of amounts of displacement of the piezoelectric displacing members along the displacement axes thereof to give an amount of displacement of the device.

摘要翻译： 压电位移装置包括多个彼此并置的纵向效应型压电位移元件，使得其位移基本上彼此平行，每个所述压电位移元件将施加到其上的电压转换为机械位移。 提供了连接器，其将压电位移构件彼此串联机械地连接并且导出压电位移构件沿其位移轴的位移量的总和，以给出装置的位移量。

公开(公告)号：US4304818A

公开(公告)日：1981-12-08

申请号：US103571

申请日：1979-12-14

申请人： Hideyo Hirata ,  Takeshi Hakamada ,  Misao Souma ,  Masao Matsui ,  Yoshiyuki Suda ,  Yoshiharu Karasawa ,  Toshikazu Narahara

发明人： Hideyo Hirata ,  Takeshi Hakamada ,  Misao Souma ,  Masao Matsui ,  Yoshiyuki Suda ,  Yoshiharu Karasawa ,  Toshikazu Narahara

IPC分类号： H02K15/12 ,  C08G18/00 ,  C08G59/40 ,  C08G73/06 ,  H01B3/30 ,  H01B3/40 ,  H02K3/30 ,  B05D5/12

CPC分类号： C08G73/06 ,  C08G18/003 ,  C08G59/4028 ,  C08G73/0638 ,  H01B3/302 ,  H01B3/303 ,  H01B3/40 ,  H02K3/30 ,  Y10T428/2936 ,  Y10T428/2964 ,  Y10T428/2969 ,  Y10T428/2971 ,  Y10T428/31511 ,  Y10T428/31533 ,  Y10T428/31547 ,  Y10T428/31551 ,  Y10T428/31562 ,  Y10T428/31601 ,  Y10T428/31721 ,  Y10T428/31725

摘要： An insulation system for winding of electric rotating machines having thermal resistance of class H or more and excellent adhesiveness between a conductor and an insulating layer and resistance to thermal stress can be produced by wrapping a plurality of layers of an insulating tape or sheet having thermal resistance of class H or more around a winding conductor, impregnating the thus treated winding conductor with a solventless varnish consisting essentially of 1 equivalent of an epoxy compound containing at least two vicinal epoxy groups, more than one equivalent of an organic polyisocyanate, and then heating the inpregnated winding conductor at a temperature above 60.degree. C. for a time sufficient to form and cure a resin containing as recurring units at least two isocyanurate rings directly bonded to one another through the residue of the polyisocyanate and two oxazolidone rings directly bonded to each other through the residue of the polyepoxide in the presence of 0.01-10% by weight of a catalyst which forms the isocyanurate rings and oxazolidone rings based on the total amount of the polyepoxide and polyisocyanate.

摘要翻译： 用于缠绕具有H级以上的耐热性和导体与绝缘层之间优异的粘合性和耐热应力的电动旋转机械的绝缘系统可以通过包裹多层绝缘带或具有热阻的片材来制造 在绕组导体周围的H级以上的等级浸渍在这样处理的绕组导体上，用无溶剂的清漆基本上由1当量的含有至少两个邻位环氧基，多于1当量的有机多异氰酸酯的环氧化合物组成，然后加热 浸渍的绕组导体在60℃以上的时间足以形成和固化含有作为重复单元的树脂的树脂，所述树脂通过多异氰酸酯的残基和彼此直接键合的两个直接键合的至少两个异氰脲酸酯环直接键合 在0.01-10重量％存在下通过聚环氧化物的残基 基于聚环氧化物和多异氰酸酯的总量形成异氰脲酸酯环和恶唑烷酮环的催化剂。

公开(公告)号：US08476641B2

公开(公告)日：2013-07-02

申请号：US12745133

申请日：2008-09-08

申请人： Yoshiyuki Suda ,  Yutaka Ota

发明人： Yoshiyuki Suda ,  Yutaka Ota

IPC分类号： H01L29/24

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L21/8213 ,  H01L27/1021 ,  H01L27/1022 ,  H01L27/24

摘要： A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.

摘要翻译： 实现高集成度以及减少读出时间的开关电阻RAM。 形成由N阱11构成的集电极构成的NPN型双极晶体管BT，在N阱11的表面形成的由P +型Si层12A构成的基极层和由N阱11的表面形成的发射极层 形成在P +型Si层12A的表面上的N +型Si层15。 而且，形成与N +型Si层15电连接的字线WL0，与字线WL0相交的位线BL1〜BL4。 此外，形成在P +型Si层12A的表面上形成的多个开关层14，其各自与对应的每个位线电连接，并且在导通状态和断开状态之间切换以及电位固定线 19A以将P +型Si层12A固定在预定电位。

公开(公告)号：US08030662B2

公开(公告)日：2011-10-04

申请号：US12745146

申请日：2008-09-08

申请人： Yoshiyuki Suda

发明人： Yoshiyuki Suda

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/35 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/24 ,  Y10S438/931

摘要： There is offered a switching resistance RAM that is very much reduced in an occupied area and is highly integrated. Memory cells CEL11-CEL14 are formed corresponding to four intersections of word lines WL0 and WL1 and bit lines BL0 and BL1. Each of the memory cells CEL11-CEL14 are composed of a switching layer 13 formed on a surface of an N+ type Si layer 11. The switching layer 13 is electrically connected to the bit line BL0 or BL1 thereabove through an electrode 14. The switching layer 13 is composed of a SiC layer 13A stacked on the surface of the N+ type Si layer 11 and a Si oxide layer 13B stacked on the SiC layer 13A. A top surface of the Si oxide layer 13B, that is the uppermost layer of the switching layer 13, is electrically connected to the corresponding bit line BL0 or BL1.

摘要翻译： 提供了一个开关电阻RAM，在占用面积上大大减少，并且高度集成。 对应于字线WL0和WL1以及位线BL0和BL1的四个交点形成存储单元CEL11-CEL14。 每个存储单元CEL11-CEL14由形成在N +型Si层11的表面上的开关层13构成。开关层13通过电极14与上述位线BL0或BL1电连接。开关层 13由层叠在N +型Si层11的表面上的SiC层13A和层叠在SiC层13A上的Si氧化物层13B构成。 作为开关层13的最上层的Si氧化物层13B的上表面电连接到对应的位线BL0或BL1。

公开(公告)号：US06838969B2

公开(公告)日：2005-01-04

申请号：US10331347

申请日：2002-12-31

申请人： Yoshiyuki Suda

发明人： Yoshiyuki Suda

IPC分类号： F16D27/14 ,  H01F5/04 ,  H01F7/06 ,  H01F27/02

CPC分类号： H01F7/06 ,  H01F5/04 ,  H01F2007/062

摘要： An electromagnet assembly for an electromagnetic apparatus has a ring member, a coil bobbin having an electrical wire wound a spool of the ring member, and a ring case. The ring member is disposed in an annular groove of the ring case. An opening is formed through the ring case adjacent to its closed end surface. A connector, which is disposed on the ring case and covers the opening, includes a case having a closed shape and a bottom, and a cap closing an open end of the case. Ends of the electrical wire and ends of a lead wire are joined in the connector. A projection portion is formed around a fringe portion of a first end surface of the cap and abuts an open end surface of the case. The cap is secured fixedly to the case after the projection portion is melted.

公开(公告)号：US4823178A

公开(公告)日：1989-04-18

申请号：US780598

申请日：1985-09-26

申请人： Yoshiyuki Suda

发明人： Yoshiyuki Suda

IPC分类号： G03G5/00 ,  H01L27/146 ,  H01L31/10 ,  H01L31/108 ,  H01L27/14

CPC分类号： H01L27/14643 ,  H01L31/108

摘要： A photosensor for realizing an image sensor which can meet the requirements of high resolution, high operation speed and high signal-to-noise ratio is disclosed. The photosensor comprises a circuit substrate, a thin film transistor formed on the circuit substrate and an amorphous silicon photodiode formed on the substrate integral with the thin transistor between the drain and gate electrodes thereof. Also formed on the circuit substrate adjacent to the thin film transistor and photodiode are a charging switch element for coupling the photodiode to a DC power source to charge an inter-electrode capacitance of the photodiode, a charge storage capacitor charged by a channel current of the thin film transistor controlled by an inter-electrode capacitance voltage of the photodiode which varies in response to incident light after the inter-electrode capacitance has been charged, and a detecting switch element for coupling the capacitor to an output amplifier. The charging and detecting switch elements are each formed of a thin film transistor.

摘要翻译： 公开了一种用于实现能够满足高分辨率，高操作速度和高信噪比要求的图像传感器的光传感器。 光电传感器包括电路基板，形成在电路基板上的薄膜晶体管和形成在其与漏极和栅电极之间的薄晶体管集成的基板上的非晶硅光电二极管。 还形成在与薄膜晶体管和光电二极管相邻的电路基板上的是充电开关元件，用于将光电二极管耦合到DC电源，以对光电二极管的电极间电容进行充电;电荷存储电容器由 由电极间电容充电后的入射光而变化的光电二极管的电极间电容电压控制的薄膜晶体管，以及用于将电容器耦合到输出放大器的检测开关元件。 充电和检测开关元件均由薄膜晶体管形成。

公开(公告)号：US20080054270A1

公开(公告)日：2008-03-06

申请号：US11725009

申请日：2007-03-16

申请人： Yoshiyuki Suda

发明人： Yoshiyuki Suda

IPC分类号： H01L29/12 ,  H01L21/31

CPC分类号： H01L21/02123 ,  H01L21/022 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/049 ,  H01L21/3165 ,  H01L21/8213 ,  H01L27/101 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/6606 ,  H01L29/8615

摘要： A semiconductor memory device that is configured with a Si substrate layer, a SiC layer and a Si oxide layer, including a structure in which the SiC layer is layered onto the Si substrate layer and the Si oxide layer is layered onto the SiC. Wherein, the Si oxide layer includes two or more layers whose compositional ratios of SiO2 are different in a direction of layers, and a compositional ratio of SiO2 in the. Si oxide layer that is distanced most from the SiC layer is more than other layers.

摘要翻译： 一种半导体存储器件，其被配置有Si衬底层，SiC层和Si氧化物层，其包括其中SiC层被层叠在Si衬底层上并且Si氧化物层被层叠在SiC上的结构。 其中，Si氧化物层包括两层以上SiO 2层的组成比在层的方向上不同的SiO 2层的组成比，SiO 2 / 与SiC层最远的Si氧化物层比其他层更多。