公开(公告)号：US20120089656A1

公开(公告)日：2012-04-12

申请号：US13301932

申请日：2011-11-22

申请人： Tetsufumi TANAMOTO ,  Mari MATSUMOTO ,  Shinobu FUJITA ,  Kazutaka IKEGAMI

发明人： Tetsufumi TANAMOTO ,  Mari MATSUMOTO ,  Shinobu FUJITA ,  Kazutaka IKEGAMI

IPC分类号： G06F7/58

CPC分类号： H03K3/84 ,  G06F7/58

摘要： A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.

摘要翻译： 随机数生成电路包括：生成并输出物理随机数的元素; 数字化电路将物理随机数字化，以输出由测试电路测试的随机数序列; 以及纠错码电路，包括具有输入的随机数序列的移位寄存器，将所存储的随机数序列乘以纠错码生成矩阵的乘法器和输出移位寄存器的输出和 根据由测试电路获得的测试结果的乘数的输出。 当由测试电路执行的测试结果指示拒绝时，纠错码电路将来自选择器开关的乘法器的输出作为校正的随机数序列输出。 当测试结果表明拒绝时，测试电路测试校正的随机数序列。

公开(公告)号：US20100073025A1

公开(公告)日：2010-03-25

申请号：US12404606

申请日：2009-03-16

申请人： Tetsufumi TANAMOTO ,  Hideyuki SUGIYAMA ,  Kazutaka IKEGAMI ,  Yoshiaki SAITO

发明人： Tetsufumi TANAMOTO ,  Hideyuki SUGIYAMA ,  Kazutaka IKEGAMI ,  Yoshiaki SAITO

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  G11C13/0002 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/18

摘要： A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.

摘要翻译： 可编程逻辑电路包括：输入电路，被配置为接收多个输入信号; 以及包括以矩阵形式布置的多个单元可编程单元的可编程单元阵列，每个单元可编程单元包括电阻改变型的第一存储器电路，包括第一晶体管和包括第二晶体管的电阻变化型的第二存储器电路 并联连接的第一和第二存储器电路，同一行上的第一晶体管的每个栅极分别接收一个输入信号，同一行上的第二晶体管的每个栅极接收一个输入信号的反相信号，第一个输出端的输出端 并且同一列上的第二存储器电路连接到公共输出线。

公开(公告)号：US20080251783A1

公开(公告)日：2008-10-16

申请号：US12143124

申请日：2008-06-20

申请人： Tetsufumi TANAMOTO ,  Shinobu Fujita

发明人： Tetsufumi TANAMOTO ,  Shinobu Fujita

IPC分类号： H01L29/00

CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

摘要翻译： 目的是提供具有较小的电路尺寸和较小的输出偏压值的随机数产生装置。 随机数产生装置包括彼此平行布置的一对第一和第二电流路径，以及一对可互相交换电荷并位于第一和第二电流路径附近的第一和第二细颗粒 。

公开(公告)号：US20120243336A1

公开(公告)日：2012-09-27

申请号：US13240087

申请日：2011-09-22

申请人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

发明人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

IPC分类号： G11C16/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

公开(公告)号：US20080251782A1

公开(公告)日：2008-10-16

申请号：US12143104

申请日：2008-06-20

申请人： Tetsufumi TANAMOTO ,  Shinobu FUJITA

发明人： Tetsufumi TANAMOTO ,  Shinobu FUJITA

IPC分类号： H01L29/06 ,  G06F7/58

CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

公开(公告)号：US20120250399A1

公开(公告)日：2012-10-04

申请号：US13403308

申请日：2012-02-23

申请人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

发明人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

IPC分类号： G11C11/16 ,  H03K19/177

CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

公开(公告)号：US20130069134A1

公开(公告)日：2013-03-21

申请号：US13608436

申请日：2012-09-10

申请人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

发明人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

IPC分类号： H01L27/11

CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

公开(公告)号：US20110194342A1

公开(公告)日：2011-08-11

申请号：US12889881

申请日：2010-09-24

申请人： Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Takao MARUKAME ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

发明人： Hideyuki SUGIYAMA ,  Tetsufumi TANAMOTO ,  Takao MARUKAME ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

IPC分类号： G11C11/14

CPC分类号： G11C14/0081

摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

公开(公告)号：US20090179667A1

公开(公告)日：2009-07-16

申请号：US12339638

申请日：2008-12-19

申请人： Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO ,  Tetsufumi TANAMOTO

发明人： Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO ,  Tetsufumi TANAMOTO

IPC分类号： H03K19/094 ,  H03K19/173

CPC分类号： H03K19/1733 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1697

摘要： It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.

摘要翻译： 可以提供可实现高集成度的可重构逻辑电路。 可重配置逻辑电路包括：多路复用器，其包括多个自旋MOSFET，每个具有包含磁性材料的源极和漏极，以及包括多个MOSFET的选择部分，并且基于控制从多个自旋MOSFET中选择自旋MOSFET 从控制线传输的数据; 确定电路，其确定由选择部分选择的所选择的自旋MOSFET的源极和漏极的磁性材料的磁化是处于第一状态还是处于第二状态; 以及第一和第二写入电路，其通过提供在选定的自旋MOSFET的源极和漏极之间流动的写入电流，将所选自旋MOSFET的源极和漏极的磁性材料的磁化分别置于第二和第一状态。