公开(公告)号：US20130200433A1

公开(公告)日：2013-08-08

申请号：US13613747

申请日：2012-09-13

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/31144 ,  H01L21/324 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78687

摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

公开(公告)号：US09059207B2

公开(公告)日：2015-06-16

申请号：US13613747

申请日：2012-09-13

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/31144 ,  H01L21/324 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78687

摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

摘要翻译： 一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，源极和漏极部分具有由多层应变通道分离的小于10nm的厚度。 SOI层的多层应变通道包括存在于SOI衬底的掩埋介电层上的第一晶格尺寸的第一层和与第一层直接接触的第二晶格尺寸的第二层 的多层应变通道部分。 功能栅极结构存在于SOI衬底的多层应变通道部分上。 具有多层通道的半导体器件也可以是finFET半导体器件。

公开(公告)号：US20130200459A1

公开(公告)日：2013-08-08

申请号：US13364850

申请日：2012-02-02

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/31144 ,  H01L21/324 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78687

摘要： A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

摘要翻译： 一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，具有由多层应变通道分离的厚度小于10nm的源极和漏极部分。SOI层的多层应变通道包括第一层 其具有存在于SOI衬底的掩埋电介质层上的第一晶格尺寸，以及与多层应变通道部分的第一层直接接触的第二晶格尺寸的第二层。 功能栅极结构存在于SOI衬底的多层应变通道部分上。 具有多层通道的半导体器件也可以是finFET半导体器件。

公开(公告)号：US20130193483A1

公开(公告)日：2013-08-01

申请号：US13359858

申请日：2012-01-27

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/7848

摘要： MOSFET structures are provided having a compressively strained silicon channel. A semiconductor device is provided that comprises a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises a channel formed below the gate stack; and a compressively strained silicon layer on at least a portion of the silicon substrate to compressively strain the channel.

摘要翻译： 提供具有压缩应变硅通道的MOSFET结构。 提供一种半导体器件，其包括在硅衬底上具有栅极堆叠的场效应晶体管（FET）结构，其中所述场效应晶体管结构包括形成在所述栅极堆叠下方的沟道; 以及在所述硅衬底的至少一部分上的压缩应变硅层，以压缩所述通道。

公开(公告)号：US20120210932A1

公开(公告)日：2012-08-23

申请号：US13032866

申请日：2011-02-23

申请人： BAHMAN HEKMATSHOAR-TABARI ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： BAHMAN HEKMATSHOAR-TABARI ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： C30B25/02 ,  C30B25/10

CPC分类号： C30B25/04 ,  C30B25/105 ,  C30B25/14 ,  C30B25/183 ,  C30B25/186 ,  C30B29/06 ,  C30B33/12 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065

摘要： An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

摘要翻译： 外延生长方法包括提供衬底材料的暴露的结晶区域。 硅在低温工艺中外延沉积在衬底材料上，其中沉积温度低于500摄氏度。 源气体用稀释气体稀释，稀释气体与原料气体的气体比小于1000。

公开(公告)号：US10011920B2

公开(公告)日：2018-07-03

申请号：US13032866

申请日：2011-02-23

申请人： Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： C30B25/04 ,  C30B25/10 ,  C30B25/14 ,  C30B29/06 ,  C30B25/18 ,  C30B33/12 ,  H01L21/02 ,  H01L21/3065

CPC分类号： C30B25/04 ,  C30B25/105 ,  C30B25/14 ,  C30B25/183 ,  C30B25/186 ,  C30B29/06 ,  C30B33/12 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065

摘要： An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

公开(公告)号：US09105775B2

公开(公告)日：2015-08-11

申请号：US13535974

申请日：2012-06-28

申请人： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/0236 ,  H01L31/0352 ,  H01L31/0725

CPC分类号： H01L31/02363 ,  H01L31/03529 ,  H01L31/0725 ,  Y02E10/50

摘要： A multi-junction photovoltaic device includes a germanium layer having pyramidal shapes with (111) facets exposed to form a textured surface. A first p-n junction is formed on or over the textured surface. Another p-n junction is formed over the first p-n junction and following the textured surface.

摘要翻译： 多结光伏器件包括具有金字塔形状的锗层，其具有暴露以形成纹理表面的（111）刻面。 在纹理表面上或上方形成第一个p-n结。 另一个p-n结形成在第一个p-n结上并跟随有纹理的表面。

公开(公告)号：US20140000687A1

公开(公告)日：2014-01-02

申请号：US13535974

申请日：2012-06-28

申请人： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/0236

CPC分类号： H01L31/02363 ,  H01L31/03529 ,  H01L31/0725 ,  Y02E10/50

摘要： A multi-junction photovoltaic device includes a germanium layer having pyramidal shapes with (111) facets exposed to form a textured surface. A first p-n junction is formed on or over the textured surface. Another p-n junction is formed over the first p-n junction and following the textured surface.

摘要翻译： 多结光伏器件包括具有金字塔形状的锗层，其具有暴露以形成纹理表面的（111）刻面。 在纹理表面上或上方形成第一个p-n结。 另一个p-n结形成在第一个p-n结上并跟随有纹理的表面。

公开(公告)号：US20130341770A1

公开(公告)日：2013-12-26

申请号：US13555271

申请日：2012-07-23

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L29/02

CPC分类号： H01L21/31155 ,  H01L21/304 ,  H01L21/7624

摘要： An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.

摘要翻译： 首先提供包括位于基底基板和顶部半导体有源层之间的掩埋绝缘体层的SOI衬底。 然后可以在顶部半导体有源层的一部分上和/或内部形成半导体器件。 掩埋绝缘体层的与埋入绝缘体层的与顶部半导体活性层形成界面的最上表面相对的最底表面可以暴露。 然后，离子可以通过掩埋绝缘体层的最底部的表面注入埋入的绝缘体层的一部分中。 将离子注入到不会干扰埋入的绝缘体层/顶部半导体有源层界面的能量范围内，同时在掩埋的绝缘体层/顶部半导体活性层界面附近保留相当薄的部分隐埋绝缘体层。

公开(公告)号：US09018517B2

公开(公告)日：2015-04-28

申请号：US13290404

申请日：2011-11-07

申请人： Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/00 ,  H01L21/00 ,  H01L31/0304 ,  H01L31/072 ,  H01L31/18

CPC分类号： H01L31/074 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/26513 ,  H01L31/02167 ,  H01L31/022425 ,  H01L31/022441 ,  H01L31/022466 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/03044 ,  H01L31/03048 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/0682 ,  H01L31/072 ,  H01L31/18 ,  H01L31/1852 ,  H01L31/1868 ,  H01L31/1884 ,  Y02E10/544

摘要： A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.

摘要翻译： 一种光电器件，包括由具有第一导电性的IV型半导体材料的吸收层提供的单结太阳能电池和具有第二导电性的III-V族半导体材料的发射极层，其中III-V族半导体材料 具有不大于50nm的厚度。