公开(公告)号：US07906860B2

公开(公告)日：2011-03-15

申请号：US11925312

申请日：2007-10-26

申请人： Thorsten Meyer ,  Markus Brunnbauer ,  Marcus Kastner ,  Stephan Bradl

发明人： Thorsten Meyer ,  Markus Brunnbauer ,  Marcus Kastner ,  Stephan Bradl

IPC分类号： H01L23/29

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

摘要翻译： 公开了一种半导体器件。 一个实施例提供了以间隔开的关系并排布置的多个半导体芯片的布置。 第一材料至少部分地填充相邻半导体芯片之间的间距。 第二材料布置在半导体芯片和第一材料上。 选择第一材料的热膨胀系数以使布置的横向热膨胀在与第一材料和半导体芯片相交的平面中适应布置在与第二材料相交的平面中的横向热膨胀。

公开(公告)号：US20090108440A1

公开(公告)日：2009-04-30

申请号：US11925312

申请日：2007-10-26

申请人： Thorsten Meyer ,  Markus Brunnbauer ,  Marcus Kastner ,  Stephan Bradl

发明人： Thorsten Meyer ,  Markus Brunnbauer ,  Marcus Kastner ,  Stephan Bradl

IPC分类号： H01L23/16 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

摘要翻译： 公开了一种半导体器件。 一个实施例提供了以间隔开的关系并排布置的多个半导体芯片的布置。 第一材料至少部分地填充相邻半导体芯片之间的间距。 第二材料布置在半导体芯片和第一材料上。 选择第一材料的热膨胀系数以使布置的横向热膨胀在与第一材料和半导体芯片相交的平面中适应布置在与第二材料相交的平面中的横向热膨胀。

公开(公告)号：US20140332937A1

公开(公告)日：2014-11-13

申请号：US14330066

申请日：2014-07-14

申请人： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

发明人： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

IPC分类号： H01L23/60 ,  H01L23/48

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

摘要翻译： 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

公开(公告)号：US20090045511A1

公开(公告)日：2009-02-19

申请号：US11839129

申请日：2007-08-15

申请人： Thorsten Meyer ,  Markus Brunnbauer ,  Stephan Bradl

发明人： Thorsten Meyer ,  Markus Brunnbauer ,  Stephan Bradl

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L23/525 ,  H01L23/5329 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line.

摘要翻译： 集成电路包括包括接触焊盘，耦合到接触焊盘的再分配线以及衬底和再分配线之间的介电材料层的衬底。 集成电路包括耦合到再分配线的焊球和密封介电材料层和再分配线的聚对二甲苯材料层。

公开(公告)号：US08309454B2

公开(公告)日：2012-11-13

申请号：US11746936

申请日：2007-05-10

申请人： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

发明人： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

IPC分类号： H01L21/4763

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

摘要翻译： 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

公开(公告)号：US07687895B2

公开(公告)日：2010-03-30

申请号：US11939938

申请日：2007-11-14

申请人： Markus Brunnbauer ,  Jens Pohl ,  Klaus Pressel ,  Thorsten Meyer ,  Recai Sezi ,  Stephan Bradl ,  Ralf Plieninger

发明人： Markus Brunnbauer ,  Jens Pohl ,  Klaus Pressel ,  Thorsten Meyer ,  Recai Sezi ,  Stephan Bradl ,  Ralf Plieninger

IPC分类号： H01L23/02 ,  H01L23/043 ,  H01L23/10 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05099

摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.

摘要翻译： 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 工件还包括布置在至少两个半导体芯片上的导电层，导电层至少布置在第二主表面的区域上，以及配置在导电层上的模塑料。 在模塑料中配置有接触孔。

公开(公告)号：US07759792B2

公开(公告)日：2010-07-20

申请号：US11839129

申请日：2007-08-15

申请人： Thorsten Meyer ,  Markus Brunnbauer ,  Stephan Bradl

发明人： Thorsten Meyer ,  Markus Brunnbauer ,  Stephan Bradl

IPC分类号： H01L23/04

CPC分类号： H01L24/11 ,  H01L23/525 ,  H01L23/5329 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line.

摘要翻译： 集成电路包括包括接触焊盘，耦合到接触焊盘的再分配线以及衬底和再分配线之间的介电材料层的衬底。 集成电路包括耦合到再分配线的焊球和密封介电材料层和再分配线的聚对二甲苯材料层。

公开(公告)号：US20080265421A1

公开(公告)日：2008-10-30

申请号：US11746936

申请日：2007-05-10

申请人： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger

发明人： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger

IPC分类号： H01L23/52 ,  H01L21/4763 ,  H01L23/552

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

摘要翻译： 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

公开(公告)号：US20080265383A1

公开(公告)日：2008-10-30

申请号：US11939938

申请日：2007-11-14

申请人： Markus Brunnbauer ,  Jens Pohl ,  Klaus Pressel ,  Thorsten Meyer ,  Recai Sezi ,  Stephan Bradl ,  Ralf Plieninger

发明人： Markus Brunnbauer ,  Jens Pohl ,  Klaus Pressel ,  Thorsten Meyer ,  Recai Sezi ,  Stephan Bradl ,  Ralf Plieninger

IPC分类号： H01L23/552 ,  H01L21/56

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05099

摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.

摘要翻译： 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。 在模塑料中配置有接触孔。

公开(公告)号：US09093322B2

公开(公告)日：2015-07-28

申请号：US11777694

申请日：2007-07-13

申请人： Thorsten Meyer ,  Markus Brunnbauer ,  Recai Sezi

发明人： Thorsten Meyer ,  Markus Brunnbauer ,  Recai Sezi

IPC分类号： H01L23/48 ,  H01L23/00 ,  B81C1/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/12 ,  B81B2207/07 ,  B81B2207/097 ,  B81C1/00301 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device is disclosed. One embodiment includes a semiconductor substrate and at least two insulating elements located above the semiconductor substrate or above a mold compound embedding the semiconductor substrate. The at least two insulating elements have a first face facing the semiconductor substrate or the mold compound and a second face facing away from the semiconductor substrate or the mold compound. A conductive element for each of the at least two insulating elements extends from the first face of the insulating element to the second face of the insulating element.

摘要翻译： 公开了一种半导体器件。 一个实施例包括半导体衬底和位于半导体衬底之上或在嵌入半导体衬底的模具化合物上方的至少两个绝缘元件。 所述至少两个绝缘元件具有面对半导体衬底或模具化合物的第一面和背离半导体衬底或模具化合物的第二面。 用于至少两个绝缘元件中的每一个的导电元件从绝缘元件的第一面延伸到绝缘元件的第二面。