公开(公告)号：US20070032094A1

公开(公告)日：2007-02-08

申请号：US11196985

申请日：2005-08-04

Applicant: Ting Tsui ,  Andrew McKerrow ,  Satyavolu Rao ,  Robert Kraft

Inventor： Ting Tsui ,  Andrew McKerrow ,  Satyavolu Rao ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/76825

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract translation: 本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。 提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或 弹性模量增加值。

公开(公告)号：US20070105368A1

公开(公告)日：2007-05-10

申请号：US11268036

申请日：2005-11-07

Applicant: Ting Tsui ,  Andrew McKerrow ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Andrew McKerrow ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/823807 ,  H01L21/3105 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823864

Abstract: The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.

Abstract translation: 本发明在一个实施例中提供了一种制造微电子器件200的方法。 该实施例包括在衬底210和栅极结构230上形成衬垫310，使衬垫310经受电子束405并在衬垫310上沉积预金属介电层415。

公开(公告)号：US07678713B2

公开(公告)日：2010-03-16

申请号：US11196985

申请日：2005-08-04

Applicant: Ting Y. Tsui ,  Andrew McKerrow ,  Satyavolu Srinivas Papa Rao ,  Robert Kraft

Inventor： Ting Y. Tsui ,  Andrew McKerrow ,  Satyavolu Srinivas Papa Rao ,  Robert Kraft

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76825

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract translation: 本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。 提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或 弹性模量增加值。

公开(公告)号：US06872665B1

公开(公告)日：2005-03-29

申请号：US09599718

申请日：2000-06-22

Applicant: Francis G. Celii ,  Guoqiang Xing ,  Andrew McKerrow ,  Andrew Ralston ,  Zhicheng Tang ,  Kenneth J. Newton ,  Robert Kraft ,  Jeff West

Inventor： Francis G. Celii ,  Guoqiang Xing ,  Andrew McKerrow ,  Andrew Ralston ,  Zhicheng Tang ,  Kenneth J. Newton ,  Robert Kraft ,  Jeff West

IPC: H01L21/768 ,  H01L21/20

CPC classification number: H01L21/76808

Abstract: A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.

Abstract translation: 用于形成互连线和通孔的双镶嵌工艺流程，其中在沟槽蚀刻之前蚀刻至少部分通孔（116）。 使用低k材料如热固性有机聚合物用于ILD（106）和IMD（110）。 在至少部分通孔蚀刻之后，BARC（120）沉积在包括在通孔（116）中的结构上。 然后，对沟槽（126）进行图案化和蚀刻。 虽然在沟槽蚀刻期间去除了至少一些BARC（120）材料，但是通孔（116）的底部被保护。

公开(公告)号：US07939400B2

公开(公告)日：2011-05-10

申请号：US12235766

申请日：2008-09-23

Applicant: Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract translation: 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US07087518B2

公开(公告)日：2006-08-08

申请号：US10438566

申请日：2003-05-15

Applicant: David Gerald Farber ,  William Wesley Dostalik ,  Robert Kraft ,  Andrew J. McKerrow ,  Kenneth Joseph Newton ,  Ting Tsui

Inventor： David Gerald Farber ,  William Wesley Dostalik ,  Robert Kraft ,  Andrew J. McKerrow ,  Kenneth Joseph Newton ,  Ting Tsui

IPC: H01L21/322

CPC classification number: H01L21/76829 ,  H01L21/306 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/76801

Abstract: One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

公开(公告)号：US20060264042A1

公开(公告)日：2006-11-23

申请号：US11134698

申请日：2005-05-20

Applicant: Laura Matz ,  Ting Tsui ,  Robert Kraft

Inventor： Laura Matz ,  Ting Tsui ,  Robert Kraft

IPC: H01L21/44

CPC classification number: H01L23/53295 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides an interconnect structure, a method of manufacture therefore, and an integrated circuit including the same. In one embodiment of the present invention, the interconnect structure includes a conductive feature (150) located in or over a dielectric layer (140), and a silicon oxycarbonitride layer (160) located over the conductive feature (150).

Abstract translation: 本发明提供互连结构，因此制造方法，以及包括其的集成电路。 在本发明的一个实施例中，互连结构包括位于介电层（140）中或上方的导电特征（150）和位于导电特征（150）之上的硅碳氮氧化物层（160）。

公开(公告)号：US20060172481A1

公开(公告)日：2006-08-03

申请号：US11049275

申请日：2005-02-02

Applicant: Ting Tsui ,  Satyavolu Papa Rao ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Satyavolu Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/469 ,  H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract translation: 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US20050255687A1

公开(公告)日：2005-11-17

申请号：US10843957

申请日：2004-05-11

Applicant: Ping Jiang ,  Hyesook Hong ,  Ting Tsui ,  Robert Kraft

Inventor： Ping Jiang ,  Hyesook Hong ,  Ting Tsui ,  Robert Kraft

IPC: H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/02123 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/76807 ,  H01L21/76808

Abstract: An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over said spin-on-glass material (step 214), patterning the photoresist layer (step 214), and etching trench spaces (step 216).

Abstract translation: 本发明的一个实施例是制造半导体晶片的方法。 该方法包括在半导体晶片上沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤210），施加 蒸发（步骤212），在旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214），然后蚀刻半导体晶片（步骤216）。 本发明的另一实施例是在半导体晶片上制造双镶嵌后端层的方法。 该方法包括在电介质层上和通孔内沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤 （步骤212），在所述旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214）和蚀刻沟槽空间（步骤216）。

公开(公告)号：US20060264028A1

公开(公告)日：2006-11-23

申请号：US11134566

申请日：2005-05-20

Applicant: Laura Matz ,  Ting Tsui ,  Robert Kraft

Inventor： Laura Matz ,  Ting Tsui ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/3105 ,  H01L21/76825 ,  H01L21/76829 ,  H01L23/5329 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a process for increasing the hermeticity of a hermetic layer, a method for manufacturing an interconnect structure, and a method for manufacturing an integrated circuit. The process for increasing the hermeticity of the hermetic layer, without limitation, includes providing a hermetic layer over a substrate (160), the hermetic layer having a initial hermeticity, and subjecting the hermetic layer to an energy beam, thereby causing the initial hermeticity to improve (170).

Abstract translation: 本发明提供一种增加气密层的气密性的方法，一种互连结构的制造方法以及集成电路的制造方法。 增加密封层的气密性而不是限制的方法包括在衬底（160）上提供密封层，密封层具有初始密封性，并且使密封层经受能量束，从而使初始气密性 改善（170）。