公开(公告)号：US20070032094A1

公开(公告)日：2007-02-08

申请号：US11196985

申请日：2005-08-04

Applicant: Ting Tsui ,  Andrew McKerrow ,  Satyavolu Rao ,  Robert Kraft

Inventor： Ting Tsui ,  Andrew McKerrow ,  Satyavolu Rao ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/76825

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract translation: 本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。 提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或 弹性模量增加值。

公开(公告)号：US20050239218A1

公开(公告)日：2005-10-27

申请号：US10829053

申请日：2004-04-21

Applicant: Sanjeev Aggarwal ,  Kelly Taylor ,  Lindsey Hall ,  Satyavolu Rao

Inventor： Sanjeev Aggarwal ,  Kelly Taylor ,  Lindsey Hall ,  Satyavolu Rao

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/3105 ,  H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11585 ,  H01L21/31053 ,  H01L27/11502 ,  H01L27/1159 ,  H01L28/55

Abstract: The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).

Abstract translation: 本发明提供一种铁电电容器及其制造方法，以及制造铁电随机存取存储器（FeRAM）器件的方法。 除了其他元件之外，铁电电容器（100）包括位于第一电极层（160）上方的基本平坦的铁电介质层（165），其中基本上平坦的铁电介质层（165）的平均表面粗糙度小于约 4nm。 铁电电容器（100）还包括位于基本上平坦的铁电介质层（165）上方的第二电极层（170）。

公开(公告)号：US20060160299A1

公开(公告)日：2006-07-20

申请号：US11037530

申请日：2005-01-18

Applicant: Satyavolu Rao ,  Darius Crenshaw ,  Stephan Grunow ,  Kenneth Brennan ,  Somit Joshi ,  Montray Leavy ,  Phillip Matz ,  Sameer Ajmera ,  Yuri Solomentsev

Inventor： Satyavolu Rao ,  Darius Crenshaw ,  Stephan Grunow ,  Kenneth Brennan ,  Somit Joshi ,  Montray Leavy ,  Phillip Matz ,  Sameer Ajmera ,  Yuri Solomentsev

IPC: H01L21/8242

CPC classification number: H01L21/76834 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76849 ,  H01L23/5223 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract translation: 公开了MIM（金属绝缘金属）电容器（164）的形成和电阻器（166）的同时形成。 在用作电容器（164）的底部电极（170）的铜沉积（110）上形成铜扩散阻挡层（124）。 铜扩散阻挡层（124）减轻了铜从铜沉积物（110）的不期望的扩散，并且通过无电沉积形成，使得在除了顶部表面（125）之外的位置处几乎不会沉积阻挡材料， 的铜/底电极的沉积。 随后，分别施加介电层（150）和导电（152）材料层以形成MIM电容器（164）的电介质（172）和顶电极（174），其中导电顶电极材料层（152） 还用于同时开发与电容器（164）相同的芯片上的电阻器（166）。

公开(公告)号：US20070117371A1

公开(公告)日：2007-05-24

申请号：US11286877

申请日：2005-11-23

Applicant: Edward Engbrecht ,  Satyavolu Rao ,  Sameer Ajmera ,  Stephan Grunow

Inventor： Edward Engbrecht ,  Satyavolu Rao ,  Sameer Ajmera ,  Stephan Grunow

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76844

Abstract: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.

Abstract translation: 装置采用具有孔密封衬垫的镶嵌层，并且包括半导体本体。 包括金属互连的金属互连层形成在半导体本体上。 介电层形成在金属互连层上。 导电沟槽特征和导电通孔特征形成在电介质层中。 孔密封衬垫仅沿着导电通孔特征的侧壁并且沿着导电沟槽特征的侧壁和底表面形成。 孔密封衬垫基本上不存在于导电通孔特征的底表面上。

公开(公告)号：US20050037613A1

公开(公告)日：2005-02-17

申请号：US10640733

申请日：2003-08-14

Applicant: Stephan Grunow ,  Satyavolu Rao ,  Noel Russell

Inventor： Stephan Grunow ,  Satyavolu Rao ,  Noel Russell

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/28556 ,  H01L21/76856

Abstract: A method for forming improved diffusion barriers for copper lines in integrated circuits is described. A low-k dielectric layer (10) is formed over a semiconductor (5). A trench (15) is formed in the low-k dielectric layer (10) and a TiNSi layer (20) is formed in the trench. An α-Ta layer (30) is formed over the TiNSi layer (20) and copper (40) is subsequently formed in the trench (15) filling the trench (15).

Abstract translation: 描述了一种用于在集成电路中形成用于铜线的改进的扩散阻挡层的方法。 在半导体（5）上形成低k电介质层（10）。 在低k电介质层（10）中形成沟槽（15），并在沟槽中形成TiNSi层（20）。 在TiNi层（20）上形成α-Ta层（30），随后在填充沟槽（15）的沟槽（15）中形成铜（40）。