公开(公告)号：US20070032094A1

公开(公告)日：2007-02-08

申请号：US11196985

申请日：2005-08-04

Applicant: Ting Tsui ,  Andrew McKerrow ,  Satyavolu Rao ,  Robert Kraft

Inventor： Ting Tsui ,  Andrew McKerrow ,  Satyavolu Rao ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/76825

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract translation: 本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。 提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或 弹性模量增加值。

公开(公告)号：US20070105368A1

公开(公告)日：2007-05-10

申请号：US11268036

申请日：2005-11-07

Applicant: Ting Tsui ,  Andrew McKerrow ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Andrew McKerrow ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/823807 ,  H01L21/3105 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823864

Abstract: The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.

Abstract translation: 本发明在一个实施例中提供了一种制造微电子器件200的方法。 该实施例包括在衬底210和栅极结构230上形成衬垫310，使衬垫310经受电子束405并在衬垫310上沉积预金属介电层415。

公开(公告)号：US20050196955A1

公开(公告)日：2005-09-08

申请号：US11114563

申请日：2005-04-25

Applicant: Ting Tsui ,  Andrew McKerrow ,  Jeannette Jacques

Inventor： Ting Tsui ,  Andrew McKerrow ,  Jeannette Jacques

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/4763

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a substrate 130. The insulating layer comprises a densified layer 140 comprising an uppermost portion 142 of the porous silicon-based dielectric layer.

Abstract translation: 本发明提供了一种用于集成电路110的绝缘层100，其包括位于衬底130上方的多孔硅基电介质层120。 绝缘层包括致密层140，其包括多孔硅基电介质层的最上部分142。

公开(公告)号：US20060264028A1

公开(公告)日：2006-11-23

申请号：US11134566

申请日：2005-05-20

Applicant: Laura Matz ,  Ting Tsui ,  Robert Kraft

Inventor： Laura Matz ,  Ting Tsui ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/3105 ,  H01L21/76825 ,  H01L21/76829 ,  H01L23/5329 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a process for increasing the hermeticity of a hermetic layer, a method for manufacturing an interconnect structure, and a method for manufacturing an integrated circuit. The process for increasing the hermeticity of the hermetic layer, without limitation, includes providing a hermetic layer over a substrate (160), the hermetic layer having a initial hermeticity, and subjecting the hermetic layer to an energy beam, thereby causing the initial hermeticity to improve (170).

Abstract translation: 本发明提供一种增加气密层的气密性的方法，一种互连结构的制造方法以及集成电路的制造方法。 增加密封层的气密性而不是限制的方法包括在衬底（160）上提供密封层，密封层具有初始密封性，并且使密封层经受能量束，从而使初始气密性 改善（170）。

公开(公告)号：US20070042599A1

公开(公告)日：2007-02-22

申请号：US11207493

申请日：2005-08-19

Applicant: Ting Tsui ,  Jeannette Jacques ,  Robert Kraft ,  Ping Jiang

Inventor： Ting Tsui ,  Jeannette Jacques ,  Robert Kraft ,  Ping Jiang

IPC: H01L21/4763

CPC classification number: H01L21/76825 ,  H01L21/76807

Abstract: A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

Abstract translation: 用基于能量的工艺制造半导体器件，其改变镶嵌工艺内的电介质层的蚀刻速率。 第一互连层形成在半导体本体上。 第一介电层形成在第一互连层上。 改变第一介电层的蚀刻速率。 在第一电介质层上形成第二电介质层。 然后改变第二电介质层的蚀刻速率。 执行沟槽蚀刻以在第二介电层内形成沟槽。 执行通孔蚀刻以在第一介电层内形成通孔腔。 空腔填充有导电材料，然后平坦化以除去多余的填充材料。

公开(公告)号：US06780756B1

公开(公告)日：2004-08-24

申请号：US10375996

申请日：2003-02-28

Applicant: David G. Farber ,  Ting Tsui ,  Robert Kraft ,  Craig Huffman

Inventor： David G. Farber ,  Ting Tsui ,  Robert Kraft ,  Craig Huffman

IPC: H01L214763

CPC classification number: H01L21/76829

Abstract: An embodiment of the invention is a metal layer 14 of a back-end module 6 where the height of the interconnects 17 is greater than the height of the dielectric regions 20. Another embodiment of the invention is a method of fabricating a semiconductor wafer 4 where the height of the interconnects 17 is greater than the height of the dielectric regions 20.

Abstract translation: 本发明的一个实施例是后端模块6的金属层14，其中互连件17的高度大于电介质区域20的高度。本发明的另一实施例是制造半导体晶片4的方法，其中 互连17的高度大于电介质区域20的高度。

公开(公告)号：US07939400B2

公开(公告)日：2011-05-10

申请号：US12235766

申请日：2008-09-23

Applicant: Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract translation: 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US07087518B2

公开(公告)日：2006-08-08

申请号：US10438566

申请日：2003-05-15

Applicant: David Gerald Farber ,  William Wesley Dostalik ,  Robert Kraft ,  Andrew J. McKerrow ,  Kenneth Joseph Newton ,  Ting Tsui

Inventor： David Gerald Farber ,  William Wesley Dostalik ,  Robert Kraft ,  Andrew J. McKerrow ,  Kenneth Joseph Newton ,  Ting Tsui

IPC: H01L21/322

CPC classification number: H01L21/76829 ,  H01L21/306 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/76801

Abstract: One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

公开(公告)号：US20060264042A1

公开(公告)日：2006-11-23

申请号：US11134698

申请日：2005-05-20

Applicant: Laura Matz ,  Ting Tsui ,  Robert Kraft

Inventor： Laura Matz ,  Ting Tsui ,  Robert Kraft

IPC: H01L21/44

CPC classification number: H01L23/53295 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides an interconnect structure, a method of manufacture therefore, and an integrated circuit including the same. In one embodiment of the present invention, the interconnect structure includes a conductive feature (150) located in or over a dielectric layer (140), and a silicon oxycarbonitride layer (160) located over the conductive feature (150).

Abstract translation: 本发明提供互连结构，因此制造方法，以及包括其的集成电路。 在本发明的一个实施例中，互连结构包括位于介电层（140）中或上方的导电特征（150）和位于导电特征（150）之上的硅碳氮氧化物层（160）。

公开(公告)号：US20060172481A1

公开(公告)日：2006-08-03

申请号：US11049275

申请日：2005-02-02

Applicant: Ting Tsui ,  Satyavolu Papa Rao ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Satyavolu Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/469 ,  H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract translation: 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。