Optical waveguides with embedded air-gap cladding layer and methods of fabrication thereof
    2.
    发明授权
    Optical waveguides with embedded air-gap cladding layer and methods of fabrication thereof 有权
    具有嵌入式气隙包覆层的光波导及其制造方法

    公开(公告)号:US06807352B2

    公开(公告)日:2004-10-19

    申请号:US10074067

    申请日:2002-02-11

    IPC分类号: G02B610

    摘要: Waveguides having air-gap cladding layers and methods of fabricating waveguides having air-gap cladding layers are disclosed. A representative waveguide includes a waveguide core having an air-gap cladding layer engaging a portion of the waveguide core. In addition, a representative method of fabricating a waveguide having an air-gap cladding layer includes: providing a substrate having a lower cladding layer disposed on the substrate; disposing a waveguide core on a portion of the lower cladding layer; disposing a sacrificial layer onto at least one portion of the lower cladding layer and the waveguide core; disposing an overcoat layer onto the lower cladding layer and the sacrificial layer; and removing the sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and engaging a portion of the waveguide core.

    摘要翻译: 公开了具有气隙包覆层的波导和制造具有气隙包覆层的波导的方法。 代表性的波导包括具有接合波导芯的一部分的气隙包覆层的波导芯。 另外,制造具有气隙包层的波导的代表性方法包括:提供具有设置在基板上的下包层的基板; 在所述下包层的一部分上设置波导芯; 在所述下包层和所述波导芯的至少一部分上设置牺牲层; 在下包层和牺牲层上设置外涂层; 以及去除所述牺牲层以在所述外涂层聚合物层内限定气隙包层并与所述波导芯的一部分接合。

    Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package
    5.
    发明授权
    Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package 失效
    引导波光学互连嵌入在微电子晶圆级批量封装内

    公开(公告)号:US06785458B2

    公开(公告)日:2004-08-31

    申请号:US10074420

    申请日:2002-02-11

    IPC分类号: G02B610

    摘要: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

    摘要翻译: 公开了具有波导的晶片级电子封装以及制造具有波导的芯片级电子封装的方法。 代表性的芯片级电子封装包括至少一个具有波导芯的波导。 此外,另一代表性的芯片级电子封装包括在波导芯的一部分周围具有气隙包覆层的波导。 用于制造芯片级电子封装的代表性方法包括:提供具有设置在基板上的钝化层的基板; 在所述钝化层的一部分上设置波导芯; 在所述钝化层和所述波导芯的至少一部分上设置第一牺牲层; 在所述钝化层和所述第一牺牲层上设置外涂层; 以及去除所述第一牺牲层以在所述外涂层聚合物层内和所述波导芯的一部分周围限定气隙包覆层。

    Back-side-of-die, through-wafer guided-wave optical clock distribution networks, method of fabrication thereof, and uses thereof
    8.
    发明授权
    Back-side-of-die, through-wafer guided-wave optical clock distribution networks, method of fabrication thereof, and uses thereof 失效
    芯片背面,贯通晶片导波光时钟分配网络,其制造方法及其应用

    公开(公告)号:US07016569B2

    公开(公告)日:2006-03-21

    申请号:US10630411

    申请日:2003-07-30

    IPC分类号: G02B6/34

    摘要: Systems and methods for back-of-die, through-wafer guided-wave optical clock distribution systems (networks) are disclosed. A representative back-of-die, through-wafer guided-wave optical clock distribution system includes an integrated circuit device with a first cladding layer disposed on the back-side of the integrated circuit device, and an core layer disposed on the first cladding layer. The core layer, the first cladding layer, or the second cladding layer can include, but is not limited to, vertical-to-horizontal input diffraction gratings, a horizontal-to-horizontal diffraction gratings, and horizontal-to-vertical output diffraction gratings.

    摘要翻译: 公开了用于芯片后晶圆导波光时钟分配系统(网络)的系统和方法。 一种代表性的芯片后晶片导波光时钟分配系统包括集成电路器件,其具有设置在集成电路器件的背面上的第一覆层,以及设置在第一覆层上的芯层 。 芯层,第一包层或第二包层可以包括但不限于垂直对水平的输入衍射光栅,水平到水平的衍射光栅和水平到垂直的输出衍射光栅 。

    Quantum mechanical semiconductor device with electron/hole diffractive
grating
    10.
    发明授权
    Quantum mechanical semiconductor device with electron/hole diffractive grating 失效
    量子机电半导体器件与电子/孔偏差光栅

    公开(公告)号:US5191216A

    公开(公告)日:1993-03-02

    申请号:US734300

    申请日:1991-07-18

    IPC分类号: H01L29/66

    CPC分类号: B82Y10/00 H01L29/66977

    摘要: A solid state, quantum mechanical electron/hole wave device in the form of a switch or multiplexor includes a layer of semiconductor material supporting substantially ballistic electron/hole transport and a periodic grating structure formed in the layer of semiconductor material, with the grating structure comprising a modulation in electron/hole potential energy and/or effective mass. Preferably, means are provided for applying and varying the grating modulation. By constructing the device to divide the input substantially completely into two output beams (to operate in the Bragg regime), a useful switch is provided. Likewise, by constructing the device to divide the input into a selected number of three or more output beams (to operate in the Raman-Nath regime), a useful multiplexor is provided.

    摘要翻译: 开关或多路复用器形式的固态,量子力学电子/空穴波器件包括支撑基本上弹道的电子/空穴传输的半导体材料层和形成在半导体材料层中的周期性光栅结构,其中光栅结构包括 电子/空穴势能和/或有效质量的调制。 优选地,提供用于施加和改变光栅调制的装置。 通过构造将输入基本上完全分成两个输出光束(以布拉格方式工作)的装置,提供有用的开关。 类似地,通过构造将输入划分为选定数量的三个或更多个输出光束(以在拉曼 - 纳思方案中操作)的装置,提供有用的多路复用器。