公开(公告)号：US5204043A

公开(公告)日：1993-04-20

申请号：US831667

申请日：1992-02-06

申请人： Toru Abiko ,  Katunobu Sakane ,  Mitsuru Harata ,  Hiroshi Yasuda

发明人： Toru Abiko ,  Katunobu Sakane ,  Mitsuru Harata ,  Hiroshi Yasuda

IPC分类号： B29C45/14

CPC分类号： B29C45/14631 ,  B29C45/14 ,  B29L2031/3047

摘要： A method of manufacturing a steering wheel, in which a coating layer is molded of a synthetic resin, by using a molding die unit, on at least the annular portion of a steering wheel core including a boss. The annular portion is located around the boss and has a groove extending in the circumferential direction thereof. Spokes couple the boss and the annular portion to each other. The method includes a die opening step in which an upper molding die and a lower molding die, which have a gate formed at the separation surfaces of the dies and communicating with the molding cavity of the die unit, are opened from each other. The second step is a core setting step in which the core is set in the cavity so that the outermost part of the groove of the annular portion having walls defining the groove between them is located as the top of the groove, one of the walls, which faces the gate and has a notched part notched to be smaller in height than the other of the walls, faces the gate at the notched part, and the top of the notched part is located below the separation surfaces. Third, a coating layer molding step is carried out in which the dies are closed on each other and the resin is injected into the cavity through the gate so that the coating layer is molded of the resin on the core. Last and a steering wheel takeout step in which the dies are opened from each other and the wheel is taken out from the dies is accomplished.

摘要翻译： 至少在包括凸台的方向盘芯的环形部分上通过使用成型模具单元来制造其中通过合成树脂模制涂层的方向盘的方法。 环形部分位于凸台周围，并且具有沿其圆周方向延伸的凹槽。 轮辐将轮毂和环形部分相互连接。 该方法包括：模具打开步骤，其中在模具的分离表面处形成有浇口并与模具单元的模腔连通的上模塑模具和下模塑模具彼此打开。 第二步是芯设置步骤，其中芯体设置在空腔中，使得具有限定它们之间的凹槽的壁的环形部分的凹槽的最外部位于凹槽的顶部，其中一个壁， 其面向门并且具有切口小于其他壁的高度的切口部分，在切口部分处面对门，并且切口部分的顶部位于分离表面下方。 第三，进行涂层成型步骤，其中模具彼此封闭，并且树脂通过浇口注入空腔，使得涂层由芯上的树脂模制而成。 最后和方向盘取出步骤，其中模具彼此打开并且车轮从模具中取出。

公开(公告)号：US5085097A

公开(公告)日：1992-02-04

申请号：US552834

申请日：1990-07-16

申请人： Mitsuru Harata ,  Hiroshi Yasuda

发明人： Mitsuru Harata ,  Hiroshi Yasuda

IPC分类号： B62D1/04 ,  C22C21/06

CPC分类号： B62D1/04 ,  C22C21/06 ,  Y10T74/20834

摘要： A steering wheel core is disclosed which comprises a boss, a core piece of a ring part disposed around the boss, and core pieces of spoke parts interconnecting the boss and the core piece of the ring part. The core pieces of the spoke parts are formed by die casting an aluminum alloy containing magnesium, iron, manganese, silicon, and unavoidable impurities. The magnesium content in the aluminum alloy is not less than 1.5% by weight and less than 2.5% by weight.

摘要翻译： 公开了一种方向盘芯，其包括凸台，设置在凸台周围的环形部件的芯部件和将凸台与环形部件的芯部相互连接的辐条部分的芯片。 辐条部件的芯片通过压铸铸造含有镁，铁，锰，硅和不可避免的杂质的铝合金形成。 铝合金中的镁含量不小于1.5重量％且小于2.5重量％。

公开(公告)号：US08536002B2

公开(公告)日：2013-09-17

申请号：US13567552

申请日：2012-08-06

申请人： Hiroshi Yasuda ,  Berthold Staufer

发明人： Hiroshi Yasuda ,  Berthold Staufer

IPC分类号： H01L21/8238

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7833

摘要： A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

摘要翻译： 通过使用非选择性外延工艺形成双极型晶体管的基极层，使得基极层在集电极有源区域上具有单一结晶区域和多晶硅层，形成包含双极晶体管和MOS晶体管的集成电路的工艺 区域，并且同时注入基极层的MOS栅极层和多晶区域，使得基极 - 集电极结延伸到小于场氧化物深度的三分之一的衬底中，并且垂直累积掺杂 基极层的多晶区域的密度在MOS栅极的垂直累积掺杂密度的80％至125％之间。 包含双极晶体管和通过所描述的工艺形成的MOS晶体管的集成电路。

公开(公告)号：US08450179B2

公开(公告)日：2013-05-28

申请号：US11670729

申请日：2007-02-02

申请人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

发明人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825 ,  H01L29/66242

摘要： A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.

摘要翻译： 一种用于制造具有相同掺杂剂类型的第一和第二双极器件的半导体器件的方法包括：在半导体层上沉积介电层，在电介质层上沉积栅极导体层，限定两个双极器件的基极区域， 栅极导体层和电介质层，在栅极导体层和基极区域的暴露的半导体层上沉积基底层，在基底层上沉积绝缘层，形成光致抗蚀剂层并限定两者的发射极区域 去除发射极区域中的光致抗蚀剂层，从而形成两个发射器窗口，掩蔽第一双极器件的发射极窗口，并将第二双极器件的基极区域中的基极层通过相关的发射极窗口暴露于另外的发射体注入 。

公开(公告)号：US08222619B2

公开(公告)日：2012-07-17

申请号：US12586717

申请日：2009-09-25

申请人： Akio Yamada ,  Hiroshi Yasuda ,  Mitsuhiro Nakano ,  Takashi Kiuchi

发明人： Akio Yamada ,  Hiroshi Yasuda ,  Mitsuhiro Nakano ,  Takashi Kiuchi

IPC分类号： A61N5/00 ,  G21G5/00

CPC分类号： B82Y40/00 ,  B82Y10/00 ,  H01J37/3045 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/24507 ,  H01J2237/24521 ,  H01J2237/24535 ,  H01J2237/24542

摘要： A multi-column electron beam exposure apparatus includes: a plurality of column cells; a wafer stage including an electron-beam-property detecting unit for measuring an electron beam property; and a controller for measuring beam properties of electron beams used in all the column cells by using the electron-beam-property detecting unit, and for adjusting the electron beams of the respective column cells so that the properties of the electron beams used in the column cells may be approximately identical. The electron beam property may be any of a beam position, a beam intensity, and a beam shape of the electron beam to be emitted. The electron-beam-property detecting unit may be a chip for calibration with a reference mark formed thereon or a Faraday cup.

摘要翻译： 多列电子束曝光装置包括：多个柱单元; 包括用于测量电子束特性的电子束特性检测单元的晶片台; 以及用于通过使用电子束特性检测单元来测量在所有列单元中使用的电子束的光束特性的控制器，并且用于调节各列电池的电子束，使得在列中使用的电子束的性质 细胞可以大致相同。 电子束特性可以是要发射的电子束的光束位置，光束强度和光束形状中的任何一个。 电子束特性检测单元可以是用于在其上形成有参考标记的校准芯片或法拉第杯。

公开(公告)号：US20110226967A1

公开(公告)日：2011-09-22

申请号：US13068995

申请日：2011-05-25

申请人： Akio Yamada ,  Tomohiro Sakazaki ,  Hiroshi Yasuda

发明人： Akio Yamada ,  Tomohiro Sakazaki ,  Hiroshi Yasuda

IPC分类号： G21K5/00

CPC分类号： H01J37/3175 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3174

摘要： An electron beam lithography apparatus includes a storage for storing data on a drawing pattern assigned a rank based on an accuracy required for a device pattern, a drawing pattern adjustment unit to generate data on divided drawing patterns based on the rank, a settlement wait time adjustment unit to determine a settlement wait time based on the rank, and a controller to draw the device pattern while irradiating an electron beam based on the data on the divided drawing patterns and the settlement wait time. The drawing pattern adjustment unit determines upper limits on the long-side length of a divided drawing pattern or on the area of the divided drawing pattern based on the rank, and divides the drawing pattern based on the upper limits.

摘要翻译： 一种电子束光刻设备，包括：存储器，用于根据设备图案所要求的准确度，对分配了等级的绘图图形进行数据存储;绘图模式调整单元，基于该等级生成分割图形的数据;结算等待时间调整 基于等级确定结算等待时间的单元，以及基于划分的绘图图案和结算等待时间的数据来照射电子束时绘制设备图案的控制器。 绘制图案调整单元基于等级来确定分割绘制图案的长边长度的上限或划分的绘制图案的区域的上限，并且基于上限划分绘图图案。

公开(公告)号：US20110057289A1

公开(公告)日：2011-03-10

申请号：US12718142

申请日：2010-03-05

申请人： Rick L. Wise ,  Hiroshi Yasuda

发明人： Rick L. Wise ,  Hiroshi Yasuda

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/36 ,  H01L21/02063 ,  H01L21/2254 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7325

摘要： An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.

摘要翻译： 一种包含双极晶体管的集成电路，其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域，以及在基极层中小于40纳米深的发射极 - 基极结。 一种形成双极晶体管的工艺，其包括在基极层和发射极层之间形成发射极掺杂剂原子层，随后进行闪光或激光退火步骤，以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

公开(公告)号：US07847272B2

公开(公告)日：2010-12-07

申请号：US11235422

申请日：2005-09-26

申请人： Hiroshi Yasuda ,  Akio Yamada

发明人： Hiroshi Yasuda ,  Akio Yamada

IPC分类号： A61N5/00

CPC分类号： H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/20 ,  H01J2237/31769

摘要： An electron beam exposure system is designed to correct a proximity effect. The electron beam exposure system includes: an electron beam generation unit for generating an electron beam; an electron beam exposure mask having opening portions that are arranged so that sizes of the opening portions change at a predetermined rate in order of arrangement; a mask deflection unit for deflecting the electron beam on the electron beam exposure mask; a substrate deflection unit for deflecting and projecting the electron beam onto a substrate; and a control unit for controlling deflection amounts in the mask deflection unit and the substrate deflection unit. The direction or directions of the change may be any one of a row direction and a column direction or may be the row and column directions.

摘要翻译： 电子束曝光系统设计用于校正邻近效应。 电子束曝光系统包括：用于产生电子束的电子束产生单元; 电子束曝光掩模，其具有开口部，其设置成使得开口部的尺寸按照布置的顺序以预定的速率变化; 用于使电子束在电子束曝光掩模上偏转的掩模偏转单元; 用于将电子束偏转和投影到衬底上的衬底偏转单元; 以及用于控制掩模偏转单元和基板偏转单元中的偏转量的控制单元。 改变的方向或方向可以是行方向和列方向中的任何一个，或者可以是行和列方向。

公开(公告)号：US07772057B2

公开(公告)日：2010-08-10

申请号：US11470760

申请日：2006-09-07

申请人： Badih El-Kareh ,  Scott Gerard Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

发明人： Badih El-Kareh ,  Scott Gerard Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

IPC分类号： H01L21/337

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0705

摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。

公开(公告)号：US07658774B2

公开(公告)日：2010-02-09

申请号：US10543699

申请日：2004-02-23

申请人： Kazutoshi Itagawa ,  Masayoshi Yuki ,  Hiroshi Yasuda ,  Yoshihiro Murata

发明人： Kazutoshi Itagawa ,  Masayoshi Yuki ,  Hiroshi Yasuda ,  Yoshihiro Murata

IPC分类号： H01M4/82 ,  H01M6/00 ,  H01M4/00 ,  H01M4/02 ,  B23P13/00

CPC分类号： H01M4/82 ,  H01M4/20 ,  H01M4/685 ,  H01M4/73 ,  H01M10/128 ,  Y10T29/10 ,  Y10T29/49108 ,  Y10T29/49114

摘要： A method of producing a grid for a lead-acid battery in accordance with the present invention includes the step of placing lead alloy foil on a base material sheet of a lead-calcium alloy and attaching the lead alloy foil under pressure to the base material sheet. The thickness t of the lead alloy foil, the thickness a of the base material sheet before the attaching, and the thickness b of the composite sheet after the attaching satisfy the relational expression 1.3≦(a+t)/b. The length L of the contact part of rollers with the base material sheet and the lead alloy foil is 10 mm or more.This makes it possible to secure good adhesion of the lead alloy foil to the base material sheet. Also, when this composite sheet is subjected to an expanding process and used as a positive electrode grid, it is possible to provide a lead-acid battery having excellent cycle life characteristics.

摘要翻译： 根据本发明的铅酸蓄电池栅格的制造方法包括将铅合金箔放置在铅 - 钙合金的基材片上并将铅合金箔在压力下附着在基材片上的工序 。 铅合金箔的厚度t，附着前的基材片的厚度a和贴附后的复合片的厚度b满足关系式1.3 <=（a + t）/ b。 与基材片和铅合金箔的辊的接触部的长度L为10mm以上。 这使得可以确保铅合金箔对基材片的良好粘附性。 此外，当该复合片材经受膨胀工艺并用作正极栅极时，可以提供具有优异的循环寿命特性的铅酸电池。