公开(公告)号：US07087967B2

公开(公告)日：2006-08-08

申请号：US10648784

申请日：2003-08-27

Applicant: Toru Mori ,  Masao Okihara ,  Shinobu Takehiro

Inventor： Toru Mori ,  Masao Okihara ,  Shinobu Takehiro

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract translation: LSI器件包括施加第一驱动电压的芯区域和施加高于上述第一驱动电压的第二驱动电压的接口区域。 LSI器件包括SOI衬底和用于将SOI衬底的SOI层分离成芯区域和界面区域的器件分离区域。 芯区域的SOI层的厚度比界面区域的SOI层的厚度薄。 LSI器件还包括形成在芯区域中的第一MOSFET，其中芯区的SOI层是完全耗尽的Si沟道，并且在界面区域中形成第二MOSFET，并且其中界面区域的SOI层是完全耗尽的 Si通道。

公开(公告)号：US06838733B2

公开(公告)日：2005-01-04

申请号：US10441040

申请日：2003-05-20

Applicant: Shinobu Takehiro

Inventor： Shinobu Takehiro

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L27/01 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L29/0649 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78603

Abstract: A semiconductor device includes a semiconductor layer formed on part of an insulating layer. The semiconductor layer includes a diffusion region and a channel region. The insulating layer is etched so that the semiconductor layer is separated from the insulating layer below at least part of the diffusion region. The space left below this part of the semiconductor layer is filled by an etch stop film that also covers the side surfaces of the insulating layer. The etch stop film prevents contact holes targeted at the diffusion region from penetrating the insulating layer due to alignment error or defects in the semiconductor layer. Since the etch stop film is not present below the channel region, the electrical characteristics of the semiconductor device are not altered.

Abstract translation: 半导体器件包括形成在绝缘层的一部分上的半导体层。 半导体层包括扩散区和沟道区。 蚀刻绝缘层，使得半导体层与扩散区域的至少一部分下方的绝缘层分离。 留在半导体层的该部分之下的空间由也覆盖绝缘层的侧表面的蚀刻停止膜填充。 蚀刻停止膜防止由于半导体层中的对准误差或缺陷导致扩散区域的接触孔穿透绝缘层。 由于蚀刻停止膜不存在于沟道区下方，因此半导体器件的电特性不会改变。

公开(公告)号：US06391797B1

公开(公告)日：2002-05-21

申请号：US08923246

申请日：1997-09-04

Applicant: Shinobu Takehiro ,  Satoshi Yamauchi ,  Masaki Yoshimaru

Inventor： Shinobu Takehiro ,  Satoshi Yamauchi ,  Masaki Yoshimaru

IPC: H01L2120

CPC classification number: H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L28/55

Abstract: A method of manufacturing a semiconductor device, comprises the following steps of growing a dielectric film made of a dielectric material whose dielectric constant is improved by crystallization thereof, on a semiconductor substrate to utilize the dielectric film as a capacitor film, and applying a voltage to the semiconductor substrate in a plasma atmosphere to increase a grown interface temperature by “dielectric heating” upon growth of the dielectric film

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上生长由电介质材料制成的电介质材料，其介电常数通过结晶而改善，以利用电介质膜作为电容器膜，并将电压施加到 半导体衬底在等离子体气氛中，通过在电介质膜生长时通过“电介质加热”来增加生长的界面温度

公开(公告)号：US20050082614A1

公开(公告)日：2005-04-21

申请号：US10982839

申请日：2004-11-08

Applicant: Shinobu Takehiro

Inventor： Shinobu Takehiro

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L27/01 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L29/0649 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78603

Abstract: A semiconductor device includes a semiconductor layer formed on part of an insulating layer. The semiconductor layer includes a diffusion region and a channel region. The insulating layer is etched so that the semiconductor layer is separated from the insulating layer below at least part of the diffusion region. The space left below this part of the semiconductor layer is filled by an etch stop film that also covers the side surfaces of the insulating layer. The etch stop film prevents contact holes targeted at the diffusion region from penetrating the insulating layer due to alignment error or defects in the semiconductor layer. Since the etch stop film is not present below the channel region, the electrical characteristics of the semiconductor device are not altered.

公开(公告)号：US5940677A

公开(公告)日：1999-08-17

申请号：US81562

申请日：1998-05-19

Applicant: Satoshi Yamauchi ,  Shinobu Takehiro ,  Masaki Yoshimaru

Inventor： Satoshi Yamauchi ,  Shinobu Takehiro ,  Masaki Yoshimaru

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/311 ,  H01L21/314 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/31111 ,  H01L28/55

Abstract: In a process where a capacitor using a BST film for a dielectric film is incorporated into a DRAM, the film is selectively removed by wet etching for forming a contact hole. For this purpose, a bottom electrode is formed and then an amorphous film is formed on the entire surface of a silicon wafer. And after forming a crystalline top electrode on this film, lamp heating is performed to crystallize only the area that is in contact with the electrode. Then wet etching is performed using a solution of hydrogen and ammonium fluoride (1:2), which allows removing only the amorphous area selectively.

Abstract translation: 在使用用于电介质膜的BST膜的电容器被并入到DRAM中的过程中，通过用于形成接触孔的湿蚀刻选择性地去除膜。 为此，形成底电极，然后在硅晶片的整个表面上形成非晶膜。 并且在该膜上形成晶体顶部电极之后，进行灯加热仅结晶与电极接触的区域。 然后使用氢和氟化铵（1：2）的溶液进行湿蚀刻，其仅允许仅选择性地去除非晶区域。

公开(公告)号：US20100181616A1

公开(公告)日：2010-07-22

申请号：US12656137

申请日：2010-01-19

Applicant: Shinobu Takehiro

Inventor： Shinobu Takehiro

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66689 ,  H01L29/7824

Abstract: A semiconductor device where a plurality of DMOS transistors formed in a distributed manner on a semiconductor substrate can operate without being destroyed and a method of manufacturing the same. The on/off threshold voltage of a DMOS transistor at the innermost position from among three or more DMOS transistors formed in a distributed manner on a semiconductor is greater than the on/off threshold voltage of a DMOS transistor at the outermost position.

Abstract translation: 在半导体基板上以分散方式形成的多个DMOS晶体管可以在不被破坏的情况下工作的半导体器件及其制造方法。 在半导体上以分布式形成的三个或更多个DMOS晶体管中的最内侧位置处的DMOS晶体管的开/关阈值电压大于最外位置的DMOS晶体管的导通/截止阈值电压。

公开(公告)号：US06794240B2

公开(公告)日：2004-09-21

申请号：US10310774

申请日：2002-12-06

Applicant: Shinobu Takehiro

Inventor： Shinobu Takehiro

IPC: H01L218242

CPC classification number: H01L28/40 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/3185

Abstract: A method of fabricating a semiconductor device wherein leakage current of a capacitor is reduced is provided. The method comprises steps of forming a lower electrode of the surface of a semiconductor substrate, forming a silicon nitride film over the lower electrode, applying a first heat treatment whereby the silicon nitride film is annealed in an atmosphere containing oxygen, forming a dielectric film containing alkaline earth metals over the silicon nitride film, applying a second heat treatment whereby the electric film is annealed in an atmosphere containing oxygen, and forming an upper electrode on the surface of the dielectric film.

Abstract translation: 提供一种制造半导体器件的方法，其中电容器的漏电流减小。 该方法包括以下步骤：形成半导体衬底的表面的下电极，在下电极上形成氮化硅膜，进行第一热处理，由此使氮化硅膜在含氧的气氛中退火，形成含有 在氮化硅膜上施加碱土金属，进行第二热处理，由此使电膜在含氧的气氛中退火，并在电介质膜的表面上形成上电极。

公开(公告)号：US06284587B1

公开(公告)日：2001-09-04

申请号：US09081567

申请日：1998-05-19

Applicant: Satoshi Yamauchi ,  Shinobu Takehiro ,  Masaki Yoshimaru

Inventor： Satoshi Yamauchi ,  Shinobu Takehiro ,  Masaki Yoshimaru

IPC: H01L218242

CPC classification number: H01L28/40 ,  H01L21/31683 ,  H01L21/76888 ,  H01L27/10852 ,  H01L28/60

Abstract: In the fabrication of capacitors, a TiO2 film is formed from a TiN film by means of heat-treatment within an atmosphere which does not contain oxygen. This serves to prevent the polysilicon which forms the bottom electrode from being oxidized during heat-treatment. Thus, once the bottom electrode has been formed on the silicon wafer, a TiN film and RuO2 film are formed, and the silicon wafer is heat-treated in an atmosphere which does not contain oxygen. In this manner, a dielectric film that is a TiO2 film and a top electrode that is a ruthenium film are obtained.

Abstract translation: 在电容器的制造中，通过在不含氧的气氛中进行热处理，由TiN膜形成TiO 2膜。 这用于防止形成底部电极的多晶硅在热处理期间被氧化。 因此，一旦在硅晶片上形成底部电极，就形成TiN膜和RuO 2膜，并且在不含氧的气氛中对硅晶片进行热处理。 以这种方式，获得作为TiO 2膜的电介质膜和作为钌膜的顶部电极。

公开(公告)号：US06284580B1

公开(公告)日：2001-09-04

申请号：US09590013

申请日：2000-06-09

Applicant: Shinobu Takehiro

Inventor： Shinobu Takehiro

IPC: H01L21336

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: In a pretreatment process, a silicon oxide film (13) with nitrogen content is formed on a semiconductor substrate (10). In a segregation process executing heat treatment in an inert gas atmosphere, a silicon nitride layer (14) segregates out at the interface of the silicon substrate (10) and the silicon oxide film (13). In a high dielectric film forming process, the unnecessary silicon oxide film (13) on the silicon nitride layer (14) is removed, a high dielectric oxide layer (15) is formed on the exposed silicon nitride layer (14). Whereby, a gate electrode (16) consisting of the silicon nitride layer (14) and the high dielectric oxide layer (15) is formed.

Abstract translation: 在预处理工艺中，在半导体衬底（10）上形成氮含量的氧化硅膜（13）。 在惰性气体气氛中进行热处理的偏析工序中，氮化硅层（14）在硅衬底（10）与氧化硅膜（13）的界面析出。 在高介电膜形成工艺中，去除氮化硅层（14）上的不需要的氧化硅膜（13），在暴露的氮化硅层（14）上形成高电介质氧化物层（15）。 由此，形成由氮化硅层（14）和高电介质氧化物层（15）构成的栅电极（16）。

公开(公告)号：US08207579B2

公开(公告)日：2012-06-26

申请号：US12656137

申请日：2010-01-19

Applicant: Shinobu Takehiro

Inventor： Shinobu Takehiro

IPC: H01L27/01

CPC classification number: H01L29/7816 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66689 ,  H01L29/7824

Abstract: A semiconductor device where a plurality of DMOS transistors formed in a distributed manner on a semiconductor substrate can operate without being destroyed and a method of manufacturing the same. The on/off threshold voltage of a DMOS transistor at the innermost position from among three or more DMOS transistors formed in a distributed manner on a semiconductor is greater than the on/off threshold voltage of a DMOS transistor at the outermost position.

Abstract translation: 在半导体基板上以分散方式形成的多个DMOS晶体管可以在不被破坏的情况下工作的半导体器件及其制造方法。 在半导体上以分布式形成的三个或更多个DMOS晶体管中的最内侧位置处的DMOS晶体管的开/关阈值电压大于最外位置的DMOS晶体管的导通/截止阈值电压。