公开(公告)号：US07087967B2

公开(公告)日：2006-08-08

申请号：US10648784

申请日：2003-08-27

Applicant: Toru Mori ,  Masao Okihara ,  Shinobu Takehiro

Inventor： Toru Mori ,  Masao Okihara ,  Shinobu Takehiro

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract translation: LSI器件包括施加第一驱动电压的芯区域和施加高于上述第一驱动电压的第二驱动电压的接口区域。 LSI器件包括SOI衬底和用于将SOI衬底的SOI层分离成芯区域和界面区域的器件分离区域。 芯区域的SOI层的厚度比界面区域的SOI层的厚度薄。 LSI器件还包括形成在芯区域中的第一MOSFET，其中芯区的SOI层是完全耗尽的Si沟道，并且在界面区域中形成第二MOSFET，并且其中界面区域的SOI层是完全耗尽的 Si通道。

公开(公告)号：US07075644B2

公开(公告)日：2006-07-11

申请号：US10629359

申请日：2003-07-29

Applicant: Toshikazu Yamamoto ,  Tsutomu Kaneko ,  Toru Mori

Inventor： Toshikazu Yamamoto ,  Tsutomu Kaneko ,  Toru Mori

IPC: G01F3/28

CPC classification number: G02B27/28 ,  G01J3/02 ,  G01J3/0224 ,  G01J2003/1286 ,  G02B5/3083 ,  G02B27/283

Abstract: A depolarizer includes a second birefringent plate having a thickness which continuously changes in a direction of an optical axis of the second birefringent plate; and a third birefringent plate having a thickness which continuously changes in a direction of 45 degree with respect to an optical axis of the third birefringent plate; wherein the second birefringent plate is stuck on the third birefringent plate so that a reduction direction of the thickness of the second birefringent plate and a reduction direction of the thickness of the third birefringent plate are opposite to each other.

Abstract translation: 消偏振器包括具有在第二双折射板的光轴方向上连续变化的厚度的第二双折射板; 以及第三双折射板，其厚度相对于所述第三双折射板的光轴在45度的方向上连续变化; 其中所述第二双折射板粘附在所述第三双折射板上，使得所述第二双折射板的厚度的减小方向和所述第三双折射板的厚度的减小方向彼此相反。

公开(公告)号：US06524905B2

公开(公告)日：2003-02-25

申请号：US09903316

申请日：2001-07-11

Applicant: Shintaro Yamamichi ,  Toru Mori ,  Akinobu Shibuya ,  Takao Yamazaki ,  Yuzo Shimada

Inventor： Shintaro Yamamichi ,  Toru Mori ,  Akinobu Shibuya ,  Takao Yamazaki ,  Yuzo Shimada

IPC: H01L218242

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L27/0688 ,  H01L2221/68363 ,  H01L2224/04042 ,  H01L2224/4847 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A semiconductor device provided with a thin film capacitor having a small equivalent series inductance is provided, which can be operated at a high frequency range and contributes to size reduction of the electronic devices. The semiconductor device comprises a device formed on a silicon substrate 1a, interlayer insulating films 3a, 3b, and 3c, wiring blocks including a power source wire block and a ground wire block, and a thin film capacitor 14 formed on an uppermost insulating layer. The thin film capacitor 14 comprises a lower electrode 6 connected to the ground wire block 4e through a contact 5d, an upper electrode 8 which is connected to the power source wire block 4d through a contact 5d, and which extends above the lower electrode 6, and a dielectric layer 7 which is inserted between the lower and the upper electrodes.

Abstract translation: 提供了具有小等效串联电感的薄膜电容器的半导体器件，其可以在高频范围下操作并且有助于电子器件的尺寸减小。 半导体器件包括形成在硅衬底1a，层间绝缘膜3a，3b和3c上的器件，包括电源线块和接地线块的布线块，以及形成在最上层绝缘层上的薄膜电容器14。 薄膜电容器14包括通过接触件5d连接到接地线块4e的下电极6，通过接触件5d连接到电源线块4d并且在下电极6上方延伸的上电极8， 以及插入在下电极和上电极之间的电介质层7。

公开(公告)号：US06239945B1

公开(公告)日：2001-05-29

申请号：US09413241

申请日：1999-10-07

Applicant: Tadashi Inoue ,  Ko ichi Nakao ,  Toru Mori

Inventor： Tadashi Inoue ,  Ko ichi Nakao ,  Toru Mori

IPC: G11B15675

CPC classification number: G11B17/046

Abstract: A disk recording or playback device comprises a holder pivoted to a chassis and reciprocatingly movable between an open position in which the holder is raised for inserting thereinto a cartridge containing a disk and a closed position in which the holder is laid on the chassis, a kickout mechanism having an engaging piece engageable with the holder and biased by a spring to urge the cartridge in a direction of discharge from the holder, the kickout mechanism extending into the holder and pushable by the insertion of the cartridge against the spring when the holder is in the open position to bring the engaging piece into engagement with the holder, and a change-over lever pivotally movably provided on the chassis for releasing the kickout mechanism from engagement with the holder during the transition of the holder from the closed position to the open position. The pivot portion of the holder and a pivot portion of the change-over lever are provided on the same surface of one member mounted on the chassis.

Abstract translation: 磁盘记录或播放装置包括一个转动到底盘的保持架，并且可在打开位置之间往复运动，在打开位置中，保持器被抬起，其中插入一个容纳盘的盒和一个关闭位置，在该位置上保持器放置在底盘上， 机构，其具有与保持器接合并且被弹簧偏压以沿着从保持器排出的方向推动盒的接合件，所述止动机构延伸到保持器中并且当保持器处于保持器时通过将盒插入弹簧推动 将接合件与保持器接合的打开位置以及可枢转地可移动地设置在底架上的转换杆，用于在保持器从关闭位置转换到打开位置期间释放脱扣机构以与保持器接合 。 保持架的枢转部分和转换杆的枢转部分设置在安装在底盘上的一个构件的相同表面上。

公开(公告)号：US5861350A

公开(公告)日：1999-01-19

申请号：US873587

申请日：1997-06-12

Applicant: Toru Mori ,  Tadahiko Horiguchi ,  Shinji Ito

Inventor： Toru Mori ,  Tadahiko Horiguchi ,  Shinji Ito

IPC: C04B35/49 ,  C04B35/493 ,  C04B35/499 ,  H01B3/12 ,  C04B35/472

CPC classification number: C04B35/499 ,  C04B35/493

Abstract: A dielectric ceramic composition is herein disclosed which comprises four lead-containing perovskite compounds of (a) lead magnesium tungstate �Pb(Mg.sub.1/2 W.sub.1/2)O.sub.3 !, (b) lead nickel niobate �Pb(Ni.sub.1/3 Nb.sub.2/3)O.sub.3 !, (c) lead titanate (PbTiO.sub.3) and (d) lead zirconate (PbZrO.sub.3) as main components and which further contains an oxide of a rare earth element; and by adjusting a molar ratio of the components (a) to (d) and an amount of the oxide of the rare earth element in specific ranges, there can be obtained the dielectric ceramic composition suitable for a dielectric substance for a multilayer ceramic capacitor which has a low firing temperature, a high dielectric constant at room temperature and a low change rate of the dielectric constant to temperature.

Abstract translation: 本文公开了一种介电陶瓷组合物，其包含四种含铅的钙钛矿化合物（a）钨酸铅镁[Pb（Mg1 / 2W1 / 2）O3]，（b）铅铌酸铅[Pb（Ni1 / 3Nb2 / 3）O3 ]，（c）钛酸铅（PbTiO 3）和（d）锆酸铅（PbZrO 3）作为主要成分，并且还含有稀土元素的氧化物; 通过调整成分（a）〜（d）的摩尔比和特定范围的稀土类元素的氧化物的量，可以得到适用于多层陶瓷电容器的电介质的电介质陶瓷组合物， 具有低的焙烧温度，室温下的高介电常数和介电常数与温度的低变化率。

公开(公告)号：US5801383A

公开(公告)日：1998-09-01

申请号：US754140

申请日：1996-11-22

Applicant: Hideo Wada ,  Mitsuhiro Nagashima ,  Naoki Oda ,  Tokuhito Sasaki ,  Toru Mori

Inventor： Hideo Wada ,  Mitsuhiro Nagashima ,  Naoki Oda ,  Tokuhito Sasaki ,  Toru Mori

IPC: G01J5/20 ,  H01L25/00 ,  G01J5/00

CPC classification number: G01J5/20

Abstract: At a heat treatment temperature in a reducing atmosphere of Ar and H.sub.2, a precursory film of V.sub.2 O.sub.5 is reduced into a VO.sub.x film with the heat treatment temperature selected in a predetermined temperature range between 350 .degree. C. and 450.degree. C., both exclusive, to control a resistivity of the VO.sub.x film, where x is greater than 1.875 and less than 2.0. The VO.sub.x film is not susceptible to a metal-semiconductor phase transition inevitable in VO.sub.2 at about 70.degree. C. and is excellent for use in a bolometer-type infrared sensor. When reduced at 350.degree. C. and 450.degree. C. the resistivity and its temperature coefficient of the VO.sub.x film at room temperature are 0.5 and 0.002 .OMEGA. cm and -2.2% and 0.2% per degree Celsius.

Abstract translation: 在Ar和H2的还原气氛中的热处理温度下，将V 2 O 5的前体膜还原成VOx膜，其中热处理温度选择在350℃至450℃的预定温度范围内， 以控制VOx膜的电阻率，其中x大于1.875且小于2.0。 VOx膜不易受到在约70℃的VO2中不可避免的金属 - 半导体相变的影响，并且适用于测辐射热计型红外传感器。 当在350℃和450℃下还原时，VOx膜在室温下的电阻率及其温度系数分别为0.5和0.002欧米加厘​​米，-2.2％和0.2％摄氏度。

公开(公告)号：US5219810A

公开(公告)日：1993-06-15

申请号：US865276

申请日：1992-04-08

Applicant: Mitsuru Furuya ,  Toru Mori ,  Atsushi Ochi

Inventor： Mitsuru Furuya ,  Toru Mori ,  Atsushi Ochi

IPC: C04B35/499 ,  H01B3/12 ,  H01G4/12

CPC classification number: H01G4/1254 ,  C04B35/499 ,  H01B3/12 ,  H01G4/1218

Abstract: A ceramic composition is herein disclosed, which is a lead-type perovskite compound capable of being subjected to low temperature-sintering among ceramic compositions for use in making capacitors, which has a high dielectric constant, low temperature-dependency thereof and a low decrease in capacitance upon application of a DC bias and which comprises a ternary system comprising lead magnesium niobate (Pb(Mg.sub.1/3 Nb.sub.2/3)O.sub.3), lead nickel niobate (Pb(Ni.sub.1/3 Nb.sub.2/3)O.sub.3) and lead titanate (PbTiO.sub.3).sub.z or a ternary system comprising lead magnesium tungstate (Pb(Mg.sub.1/2 W.sub.1/2)O.sub.3) lead titanate (PbTiO.sub.3) and lead nickel niobate (Pb(Ni.sub.1/3 Nb.sub.2/3)O.sub.3) and a desired amount of lanthanum manganese niobate La(Mn.sub.2/3 Nb.sub.1/3)O.sub.3) incorporated into the ternary system or a predetermined amount of La.sup.3+ or Ca.sup.2+ ions with which the Pb.sup.2+ ions present in the ternary system are substituted.

Abstract translation: 本文公开了一种陶瓷组合物，其是能够在用于制造电容器的陶瓷组合物中进行低温烧结的铅型钙钛矿化合物，其具有高介电常数，低温依赖性和低降低 包含铌酸铅镁（Pb（Mg1 / 3Nb2 / 3）O3），铌酸铅镍（Pb（Ni1 / 3Nb2 / 3）O3）和钛酸铅（PbTiO3）z的三元体系， 或包含钨酸铅镁（Pb（Mg1 / 2W1 / 2）O3）钛酸铅（PbTiO3）和铌酸铅镍（Pb（Ni1 / 3Nb2 / 3）O3）和所需量的铌酸镧镧（Mn2 / 3Nb1 / 3）O3）或三元体系中存在的Pb 2+离子的预定量的La 3+或Ca 2+离子被取代。

公开(公告)号：US4746721A

公开(公告)日：1988-05-24

申请号：US893206

申请日：1986-08-05

Applicant: Ryuzo Ueno ,  Yoshiyasu Masada ,  Taihei Hamasaki ,  Toru Mori

Inventor： Ryuzo Ueno ,  Yoshiyasu Masada ,  Taihei Hamasaki ,  Toru Mori

IPC: C08G63/60 ,  C08G63/66 ,  C08G63/682 ,  C08G63/688 ,  C08G63/02

CPC classification number: C08G63/66 ,  C08G63/60 ,  C08G63/682 ,  C08G63/688

Abstract: A melt-processable copolyester composed of the following structural units (I), (II) and (III) and/or (IV) as main structural components, whereinunit (I) is represented by the formula ##STR1## wherein X.sub.1, X.sub.2, X.sub.3 and X.sub.4, independently from each other, represent H, F, Cl, Br, CH.sub.3 or C(CH.sub.3).sub.3, provided that X.sub.1 to X.sub.4 do not simultaneously represent H, and n is 2 or 4,unit (II) is at least one unit selected from the group consisting of ##STR2## wherein at least one of the hydrogen atoms in each aromatic ring in units (II), (III) and (IV) may be substituted by an alkyl or alkoxy group having 1 to 4 carbon atoms or a halogen atom.The proportion of unit (I) is 2.5 to 35 mole %, the proportion of unit (II) is 2.5 to 35 mole %, and the proportion of unit (III), (IV) or a combination of units (III) and (IV) is 30 to 95 mole %.

Abstract translation: 由以下结构单元（I），（II）和（III）和/或（IV）作为主要结构组分组成的可熔融加工的共聚酯，其中单元（I）由下式表示：其中X1，X2 ，X3和X4彼此独立地表示H，F，Cl，Br，CH3或C（CH3）3，条件是X1至X4不同时表示H，n为2或4，单元（II）为 选自由 + TR 组成的组中的至少一个单元，其中每个芳环中的至少一个氢原子单元 （II），（III）和（IV）可以被具有1至4个碳原子的烷基或烷氧基或卤素原子取代。 单位（I）的比例为2.5〜35摩尔％，单位（II）的比例为2.5〜35摩尔％，单位（III），（IV）或单位（三）和（ IV）为30〜95摩尔％。

公开(公告)号：US20110263338A1

公开(公告)日：2011-10-27

申请号：US13141981

申请日：2009-11-09

Applicant: Satoshi Horie ,  Atsushi Ueno ,  Toru Mori ,  Yuichiro Murotsuka ,  Masahiro Mihara

Inventor： Satoshi Horie ,  Atsushi Ueno ,  Toru Mori ,  Yuichiro Murotsuka ,  Masahiro Mihara

IPC: A63F13/10

CPC classification number: A63F1/04 ,  A63F2009/2407 ,  A63F2009/241 ,  A63F2009/2438 ,  A63F2009/2458 ,  A63F2009/246 ,  A63F2009/2486

Abstract: To provide a game device that can reduce the size of the device and can execute the simulation of a match game scene based on an operation input by a game player.A field panel 9 imitating a field of a sporting event, card holding stages 10 that are arranged in the locations indicating the positions of players in the sporting event on the field panel 9, and holding card 11 in a raised state, a card information reading means for reading card information recorded on the cards 11 held by the card holding stages 10, and a game execution control means for controlling the execution of a game are provided. Further, the game execution control means includes a means for controlling, based on the card information read by the card information reading means, the execution of the simulation of the match game scene, which is displayed on the touch panel 6 based on the operation by the game player, to be a predetermined number of times that is set in advance.

Abstract translation: 提供可以减小设备尺寸并且可以基于游戏者输入的操作来执行匹配游戏场景的模拟的游戏装置。 模拟体育赛事的场地的场地面板9，布置在场​​地面板9上的运动事件中的玩家的位置的位置的卡片保持台10以及升起的状态下的卡11，卡片信息读取 用于读取由卡保持台10保持的卡片11上记录的卡信息的装置，以及用于控制游戏执行的游戏执行控制装置。 此外，游戏执行控制装置包括一种装置，用于根据由卡片信息读取装置读取的卡片信息，根据触摸板6的操作显示在游戏场景中的模拟， 该游戏者为预先设定的预定次数。

公开(公告)号：US20050205935A1

公开(公告)日：2005-09-22

申请号：US11134391

申请日：2005-05-23

Applicant: Toru Mori

Inventor： Toru Mori

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/417 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/66772 ,  H01L29/41733 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing method for an SOI semiconductor device includes creating transistors and an element isolation region on a semiconductor layer in an SOI substrate. The method also includes covering the transistors and the element isolation region with a first insulation film. The method also includes creating a first opening section which penetrates the first insulation film, element isolation region and a buried oxide film to expose the support substrate. The method also includes creating a first source interconnect, first drain interconnect and first gate interconnect which are electrically connected to the transistors, on the second insulation film. The method also includes forming dummy interconnects which are connected with these interconnects, and are electrically connected with the support substrate via the first opening section, on the second insulation film. The method also includes disconnecting the dummy interconnects to electrically insulate the first source interconnect, first drain interconnect and first gate interconnect from the support substrate.

Abstract translation: SOI半导体器件的制造方法包括在SOI衬底中的半导体层上产生晶体管和元件隔离区域。 该方法还包括用第一绝缘膜覆盖晶体管和元件隔离区域。 该方法还包括形成穿透第一绝缘膜，元件隔离区域和掩埋氧化膜以暴露支撑衬底的第一开口部分。 该方法还包括在第二绝缘膜上形成电连接到晶体管的第一源极互连，第一漏极互连和第一栅极互连。 该方法还包括形成与这些互连连接的虚拟互连件，并且经由第一开口部分在第二绝缘膜上与支撑基板电连接。 该方法还包括断开虚拟互连以将第一源互连，第一漏互连和第一栅互连与支撑衬底电绝缘。