-
公开(公告)号：US5767695A
公开(公告)日：1998-06-16
申请号：US747208
申请日：1996-11-12
CPC分类号： G06F13/4086 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.
-
2.发明授权
公开(公告)号：US5852728A
公开(公告)日：1998-12-22
申请号：US585344
申请日：1996-01-11
申请人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
发明人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/1679 , G06F11/20
摘要： The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.
摘要翻译： 本发明涉及双时钟源中的任何一个时钟源的时钟源切换，而不会影响双系统中的时钟输出，从而防止其中的处理器的故障。 在本发明的容错计算机系统中，多个处理单元中的每一个包括时钟源，时钟选择器，时钟停止检测单元，时钟相位调整单元和相位一致检测/操作抑制/复位单元，由此 在时钟故障的情况下，当从故障时钟源切换到正常时钟源时，时钟相位调整单元确保输出时钟信号的连续性。 设置在时钟选择器的后续级中的时钟相位调整单元插入具有通过降低其环路滤波器的增益而获得的过阻抗响应特性的PLL电路。
-
3.发明授权Data bus circuit and method of changing over termination resistor of the data bus circuit 失效数据总线电路和数据总线电路终端电阻的切换方法
公开(公告)号：US5802390A
公开(公告)日：1998-09-01
申请号：US411461
申请日：1995-03-28
申请人： Kenji Kashiwagi , Akira Yamagiwa , Masao Inoue
发明人： Kenji Kashiwagi , Akira Yamagiwa , Masao Inoue
CPC分类号： G06F13/4077 , Y02B60/1228 , Y02B60/1235
摘要： A data bus circuit includes a plurality of data buses, a plurality of data processing units connected to each of the data buses for performing transmission and reception of data in response to a transmission control signal, at least a termination resistor connected to termination of the plurality of data buses, the termination resistor including a first resistance circuit for suppressing reflection of signals on the plurality of data buses upon transmission and reception of data of the plurality of data processing units and a second resistance circuit having a resistance value larger than that of the first resistance circuit, an output control circuit for producing the transmission control signal as to whether the plurality of data processing units perform transmission and reception of data or not, and a changing-over circuit for changing over to connect the first resistance circuit to the data buses through which transmission and reception of data is performed when at least one of the plurality of data processing units performs transmission and reception of data in response to the transmission control signal and to connect the second resistance circuit to the data buses through which transmission and reception of data is not performed when any of the plurality of data processing units does not perform transmission and reception of data, whereby a current flowing in the termination resistor can be reduced when data is not transmitted on the data bus and the low power consumption of the data bus circuit can be attained.
摘要翻译： 数据总线电路包括多个数据总线，连接到每个数据总线的多个数据处理单元，用于响应于传输控制信号执行数据的发送和接收，至少连接到多个终端的终端电阻器 的数据总线，所述终端电阻器包括用于在发送和接收所述多个数据处理单元的数据时抑制所述多个数据总线上的信号的反射的第一电阻电路和具有大于所述多个数据总线的电阻值的电阻值的第二电阻电路 第一电阻电路，用于产生关于多个数据处理单元是否执行数据的发送和接收的传输控制信号的输出控制电路和用于切换以将第一电阻电路连接到数据的转换电路 当至少其中之一执行数据传输和接收时的总线 多个数据处理单元响应于传输控制信号执行数据的发送和接收，并且当多个数据处理单元中的任何一个没有执行时，将第二电阻电路连接到数据总线，通过该数据总线不执行数据的发送和接收 执行数据的发送和接收，从而当数据总线上不发送数据时可以减少在终端电阻器中流动的电流，并且可以实现数据总线电路的低功耗。
-
公开(公告)号：US5634042A
公开(公告)日：1997-05-27
申请号：US365005
申请日：1994-12-28
CPC分类号： G06F13/4239
摘要： A data transfer apparatus transfers data between a source and a destination on a clock having a phase with a signal delay over a connection line taken into account to allow a plurality of destinations to capture the transfer data on the same clock timing. Optimized data transfer and high-speed data transfer are thus realized, which in turn significantly enhances the performance of the data transfer apparatus.
摘要翻译： 数据传送装置在通过考虑的连接线具有信号延迟的相位的时钟上在源和目的地之间传送数据，以允许多个目的地在相同的时钟定时捕获传输数据。 因此实现了优化的数据传输和高速数据传输，这又显着增强了数据传送装置的性能。
-
公开(公告)号：US06985111B2
公开(公告)日：2006-01-10
申请号：US10717192
申请日：2003-11-20
IPC分类号： H01Q1/24
CPC分类号： H01Q1/526 , H05K1/0218 , H05K1/0237 , H05K1/141 , H05K2201/09309 , H05K2201/09618
摘要： A printed circuit board with reduced noise effects and without the need to increase the distance between a noise source and a wireless communication board. The circuit board includes multilayer structural conductive layers having a first conductive plane connected to power supply potential and a second conductive plane connected to ground potential. The first and second conductive planes are formed such that an electric field generated by a potential difference between the first conductive plane and the second conductive plane is concentrated on one side of one of the first conductive plane and the second conductive plane. The conductive plane associated with the concentrated electric field and the wireless communication board are on different sides relative to the conductive plane that is not associated with the concentrated electric field.
摘要翻译： 一种印刷电路板，具有降低的噪音影响，无需增加噪声源与无线通信板之间的距离。 电路板包括具有连接到电源电位的第一导电平面和连接到地电势的第二导电平面的多层结构导电层。 第一和第二导电平面形成为使得由第一导电平面和第二导电平面之间的电位差产生的电场集中在第一导电平面和第二导电平面之一的一侧。 与集中电场相关联的导电平面和无线通信板相对于与集中电场不相关的导电平面在不同的一侧。
-
公开(公告)号：US09024196B2
公开(公告)日：2015-05-05
申请号：US12985765
申请日：2011-01-06
CPC分类号： H05K1/0248 , H05K1/0245 , H05K1/025 , H05K2201/09263 , H05K2201/09727
摘要： There is provided a printed circuit board having a differential signal transmission line composed of non-skew-adjusting portions and skew-adjusting portions. The non-skew-adjusting portion consists of parallel conductive traces spaced apart by a spacing. The skew-adjusting portion consists of a pair of meander traces for the skew adjustment. The skew-adjusting portion include convex transmission line segments and concave transmission line segments. The convex transmission line segment has parallel traces having a differential trace pair spacing greater than the differential trace pair spacing in the non-skew-adjusting portion. The concave transmission line segment has parallel traces having a differential trace pair spacing smaller than the differential trace pair spacing in the non-skew-adjusting portion.
摘要翻译： 提供一种印刷电路板，其具有由非偏斜调整部分和偏斜调节部分组成的差分信号传输线。 非偏斜调节部分由间隔开的平行导电迹线组成。 偏斜调节部分由一对弯曲迹线组成，用于偏斜调整。 偏斜调整部分包括凸传输线段和凹传输线段。 凸形传输线段具有平行迹线，其具有大于非偏斜调整部分中的差分迹线对间隔的差分迹线对间隔。 凹形传输线段具有在非偏斜调节部分中具有小于差分迹线对间隔的差分迹线对间隔的平行迹线。
-
公开(公告)号：US20120208720A1
公开(公告)日：2012-08-16
申请号：US13502487
申请日：2010-10-21
申请人： Kenji Kashiwagi , Patrick C. Reid
发明人： Kenji Kashiwagi , Patrick C. Reid
CPC分类号： C12N15/1062 , C40B40/08 , C40B50/06
摘要： Provided are linkers suitable for preparing a conjugate of a nucleic acid and a peptide as a translation product thereof in a reconstituted cell-free translation system in genotype-phenotype mapping (display methods), said linkers comprising a single-stranded structure region having a side chain base pairing with the base at the 3′-end of an mRNA at one end and a peptidyl acceptor region containing an amino acid attached to an oligo RNA consisting of a nucleotide sequence of ACCA via an ester bond at the other end, characterized in that the ester bond is formed by using an artificial RNA catalyst. Also provided are display methods using [mRNA]-[linker]-[peptide] conjugates assembled via such linkers.
摘要翻译： 提供了适合于在基因型 - 表型定位（显示方法）的重建无细胞翻译系统中制备核酸和肽作为其翻译产物的缀合物的接头，所述接头包含具有侧面的单链结构区域 在一端的mRNA的3'-末端与碱基配对的链碱基和含有通过另一端通过酯键由ACCA的核苷酸序列连接的寡核苷酸连接的氨基酸的肽基受体区域，其特征在于 通过使用人造RNA催化剂形成酯键。 还提供了使用通过这种接头组装的[mRNA] - [接头] - [肽]缀合物的显示方法。
-
公开(公告)号：US08745275B2
公开(公告)日：2014-06-03
申请号：US13209994
申请日：2011-08-15
IPC分类号： G06F3/00
CPC分类号： G06F15/7803
摘要： A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the SMP virtual connecting unit is provided within the firmware.
摘要翻译： 一种刀片服务器装置，包括多个服务器模块，用于在其上安装多个服务器模块的背板以及具有连接到多个服务器模块的SMP的布线的SMP耦合装置。 每个服务器模块具有由固件控制的一个或多个处理器和用于管理其自己的服务器模块的模块管理器，模块管理器具有用于向每个处理器通知处理器ID的ID确定器，每个处理器具有处理单元和SMP虚拟 连接单元，用于指示要发送从处理单元接收到的分组的SMP耦合设备的布线，以及用于将处理器ID转换并通知给SMP虚拟连接单元的ID转换器设置在固件内 。
-
公开(公告)号：US20140086973A1
公开(公告)日：2014-03-27
申请号：US14110248
申请日：2012-03-23
IPC分类号： A61K9/70 , A61K9/00 , A61K31/5575 , A61K47/36 , A61K47/32
CPC分类号： A61K9/7007 , A61K9/0048 , A61K9/0051 , A61K31/5575 , A61K45/06 , A61K47/32 , A61K47/36
摘要： The present invention provides a pharmaceutical preparation comprising a layer-by-layer thin film that is produced by alternately layering a polycation and a polyanion, and a drug loaded onto the layer-by-layer thin film. As a result, a pharmaceutical preparation with a prolonged duration of drug action with a single dose is provided.
摘要翻译： 本发明提供一种药物制剂，其包含通过交替层叠聚阳离子和聚阴离子而制备的层状薄膜，以及负载在层叠薄膜上的药物。 结果，提供了具有单次剂量的药物作用持续时间长的药物制剂。
-
10.发明授权公开(公告)号：US07133378B2
公开(公告)日：2006-11-07
申请号：US09978554
申请日：2001-10-18
申请人： Kenji Kashiwagi , Hitoshi Yokota , Kenichi Yoshida
发明人： Kenji Kashiwagi , Hitoshi Yokota , Kenichi Yoshida
IPC分类号： H04Q7/00
摘要： A wireless LAN system is provided to make a frequency band setup task easy such that interference among base stations is reduced. The base station connected to a wired LAN includes a wired connection unit connected to the wired LAN and a wireless communication unit communicating with a LAN terminal via radio waves. The base station finds frequency bands already used by other devices in a place where the base station is installed and sets up a frequency band not used by the other devices as a frequency band to be used by the wireless communication unit to automatically set up a frequency band of radio waves to be used by the wireless communication unit.
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.036 秒)
