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    Semiconductor structure having sets of III-V compound layers and method of forming the same
    3.
    发明授权
    Semiconductor structure having sets of III-V compound layers and method of forming the same 有权
    具有III-V族化合物层的半导体结构及其形成方法

    公开(公告)号：US09142407B2

    公开(公告)日：2015-09-22

    申请号：US13743045

    申请日：2013-01-16

    申请人： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/15 ,  H01L29/20

    CPC分类号： H01L21/02507 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7787

    摘要： A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping.

    摘要翻译： 半导体结构包括衬底，在衬底上的第一III-V化合物层，在第一III-V化合物层上的一组或多组III-V化合物层，在一个或多个组上的第二III-V化合物层 的III-V化合物层，以及在第二III-V化合物层上的活性层。 第一III-V族化合物层具有第一种掺杂。 一组或多组III-V化合物层中的每一个在下III-V化合物层上包括下III-V化合物层和上III-V化合物层。 具有第一类掺杂的上III-V化合物层和下III-V族化合物层是至少一种未掺杂的，无意掺杂的具有第二类型掺杂或掺杂具有第二类掺杂的至少一种。 第二III-V族化合物层是未掺杂的或无意掺杂的，具有第二种掺杂。

    Method and Apparatus for Forming a III-V Family Layer
    5.
    发明申请
    Method and Apparatus for Forming a III-V Family Layer 审中-公开
    用于形成III-V族层的方法和装置

    公开(公告)号：US20120238076A1

    公开(公告)日：2012-09-20

    申请号：US13482029

    申请日：2012-05-29

    申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

    发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

    IPC分类号： H01L21/20

    CPC分类号： C23C16/303 ,  C23C16/4401 ,  C23C16/54 ,  C23C16/56

    摘要： Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool.

    摘要翻译： 提供了一种装置。 该装置包括：第一沉积部件，其可操作以在半导体晶片上形成化合物，所述化合物包括III族元素和V族元素中的至少一种; 第二沉积组分，其可操作以在所述化合物上形成钝化层; 以及可操作以在所述第一和第二沉积部件之间移动所述半导体晶片的转移部件，所述转移部件包围基本上不含氧且基本上不含硅的空间; 其中装载部件，第一和第二沉积部件以及传送部件都被集成到单个制造工具中。

    Split-gate memory cells and fabrication methods thereof
    6.
    发明申请
    Split-gate memory cells and fabrication methods thereof 有权
    分离栅存储单元及其制造方法

    公开(公告)号：US20080121975A1

    公开(公告)日：2008-05-29

    申请号：US11592290

    申请日：2006-11-03

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Split-gate memory cells and fabrication methods thereof
    7.
    发明申请
    Split-gate memory cells and fabrication methods thereof 失效
    分离栅存储单元及其制造方法

    公开(公告)号：US20080105917A1

    公开(公告)日：2008-05-08

    申请号：US11785382

    申请日：2007-04-17

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Semiconductor device having substantially planar contacts and body
    10.
    发明授权
    Semiconductor device having substantially planar contacts and body 有权
    具有基本上平面的触点和主体的半导体器件

    公开(公告)号：US07906418B2

    公开(公告)日：2011-03-15

    申请号：US10727272

    申请日：2003-12-03

    申请人： Chung-Yi Yu ,  Chi-Hsin Lo ,  Chia Shiung Tsai

    发明人： Chung-Yi Yu ,  Chi-Hsin Lo ,  Chia Shiung Tsai

    IPC分类号： H01L21/3205

    CPC分类号： H01L27/11521 ,  H01L23/485 ,  H01L27/115 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device, wherein a gate structure is formed over a substrate, an interconnect layer is formed over the gate structure and the substrate, and a cap layer is formed over the interconnect layer. The interconnect layer and the cap layer are then planarized to form a substantially planar surface. A mask layer, such as an oxide mask layer, is formed over the planarized portions of the interconnect layer, and the planarized cap layer and portions of the interconnect layer are removed by etching around the mask layer.

    摘要翻译： 一种制造半导体器件的方法，其中在衬底上形成栅极结构，在所述栅极结构和所述衬底之上形成互连层，并且在所述互连层上形成覆盖层。 然后将互连层和覆盖层平坦化以形成基本平坦的表面。 在互连层的平坦化部分上形成掩模层，例如氧化物掩模层，并且通过围绕掩模层进行蚀刻来去除平坦化的覆盖层和互连层的部分。