公开(公告)号：US08455319B2

公开(公告)日：2013-06-04

申请号：US13039523

申请日：2011-03-03

申请人： Tzung Han Lee ,  Chung-Yuan Lee ,  Hsien-Wen Liu

发明人： Tzung Han Lee ,  Chung-Yuan Lee ,  Hsien-Wen Liu

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/10802 ,  H01L29/7841

摘要： A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.

摘要翻译： 一种用于随机存取存储器的垂直晶体管的制造方法，具有以下步骤：在半导体衬底上限定有源区; 在活性区域外形成浅沟槽隔离结构; 蚀刻有源区并在其上形成栅介电层和定位栅，形成垂直于定位栅的字线; 在字线的外表面上形成间隔层; 将离子注入所形成的结构中，以在所述有源区域的字线的相对侧上形成n型和p型区域; 在n型和p型区域分别形成n型和p型浮体; 形成垂直于字线并连接到n型浮体的源极线; 形成垂直于源极线并连接到p型浮体的位线。 因此，实现了具有稳定阈值电压的垂直晶体管。

公开(公告)号：US08431933B2

公开(公告)日：2013-04-30

申请号：US12874232

申请日：2010-09-02

申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC分类号： H01L29/10

CPC分类号： H01L29/4983 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/4236

摘要： A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

摘要翻译： 公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉 位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸 （边缘壁），以执行侧壁接触。 自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

公开(公告)号：US08283709B2

公开(公告)日：2012-10-09

申请号：US12899721

申请日：2010-10-07

申请人： Tzung Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

发明人： Tzung Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC分类号： H01L29/772

CPC分类号： H01L21/76224 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.

摘要翻译： 公开了一种半导体器件，其包括硅化物衬底，氮化物层，两个STI和应变氮化物。 硅化物衬底具有两个掺杂区域。 氮化物层沉积在硅化物衬底上。 硅化物衬底和氮化物层具有贯穿的凹槽。 两个掺杂区位于凹槽的两侧。 凹部的端部具有比凹部大的蚀刻空间。 硅化物衬底的顶部具有鳍状结构。 两个STI位于硅化物衬底（凹槽）的两个相对侧。 应变氮化物在凹槽​​中间隔形成并附着到硅化物衬底，氮化物层，两个STI的侧壁上。 两个掺杂区域覆盖了应变氮化物。 结果，提高了半导体的效率，并且提高了驱动电流。

公开(公告)号：US20120012907A1

公开(公告)日：2012-01-19

申请号：US12874232

申请日：2010-09-02

申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC分类号： H01L27/108

CPC分类号： H01L29/4983 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/4236

摘要： A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

摘要翻译： 公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉 位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸 （边缘壁），以执行侧壁接触。 自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

公开(公告)号：US08912595B2

公开(公告)日：2014-12-16

申请号：US13106852

申请日：2011-05-12

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/308

CPC分类号： H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.

摘要翻译： 公开了一种沟槽MOS结构。 沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 沟槽栅极部分地设置在掺杂区域中。 沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。 两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

公开(公告)号：US08816715B2

公开(公告)日：2014-08-26

申请号：US13105913

申请日：2011-05-12

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L21/66 ,  G01R31/28

CPC分类号： H01L22/34 ,  G01R31/02 ,  G01R31/26 ,  G01R31/2644 ,  G01R31/2831

摘要： A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

摘要翻译： 公开了MOS测试结构。 划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。 外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。 第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。 导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接 到外延层，使得测试通孔能够一起测试外延层和衬底。

公开(公告)号：US08807429B2

公开(公告)日：2014-08-19

申请号：US13525310

申请日：2012-06-16

申请人： Hsien-Wen Liu

发明人： Hsien-Wen Liu

IPC分类号： G06Q90/00

CPC分类号： G06K19/07786 ,  H01Q1/2216 ,  H04B5/0062 ,  H04B7/10

摘要： A recognition system is offered. The recognition system is for sensing a plurality of units under test of at least an object under test. The recognition system comprises a periodic guided-wave structure and a near field sensing device. The periodic guided-wave structure is disposed under the object under test and has a plurality of conductive units periodically arranged on a plane. The near field sensing device has a near field antenna and senses the plurality of units under test through detecting the near field magnetic field. The periodic guided-wave structure confines the electromagnetic field for facilitating to determine the distance from any one of the units under test to the periodic guided-wave structure.

摘要翻译： 提供识别系统。 识别系统用于感测至少被测物体被测试的多个单元。 识别系统包括周期性导波结构和近场感测装置。 周期性导波结构设置在被测物体的下方，并且具有周期性地布置在平面上的多个导电单元。 近场感测装置具有近场天线，并且通过检测近场磁场来感测被测试的多个单元。 周期导波结构限制电磁场，以便于确定从被测单元中的任一个到周期性导波结构的距离。

公开(公告)号：US08710941B2

公开(公告)日：2014-04-29

申请号：US13020444

申请日：2011-02-03

申请人： Chien-Chih Lee ,  Wei-Chin Hsu ,  Hsien-Wen Liu

发明人： Chien-Chih Lee ,  Wei-Chin Hsu ,  Hsien-Wen Liu

IPC分类号： H01P1/205 ,  H01P7/04

CPC分类号： H01P1/205 ,  H01P1/2053 ,  H01P7/04

摘要： A high-order harmonic device of a cavity filter including a base and a lid cover the base is disclosed. The base has a through groove connecting to an upper and a lower portion. The base has a plurality of output terminal with metallic conductor extending into the inner side formed on the surface of the sidewall. The base has resonance space formed indented to receive the metallic conductor and extending to connect to the through groove. The lid has a plurality of threading holes formed corresponding to chambers and partitions received with adjusting elements for height adjustment. The adjusting elements has the resonance bars corresponding to every chamber and the suppressing bars corresponding to every partition. By adjusting suppressing bar and the partition to a predetermined distance, the space of the channel for transmitting the high-order harmonic wave can be reduced to suppress noise produced by high-order harmonic wave.

摘要翻译： 公开了一种包括基座和盖子覆盖基座的空腔滤波器的高次谐波装置。 基部具有连接到上部和下部的通孔。 基座具有多个输出端子，金属导体延伸到形成在侧壁表面上的内侧。 底座具有形成为凹入的谐振空间，用于容纳金属导体并延伸以连接到通孔。 所述盖具有多个对应于室和隔板形成的穿孔，所述隔间和隔板被接纳有用于高度调节的调节元件。 调节元件具有对应于每个室的共振杆和对应于每个分区的抑制棒。 通过将抑制棒和隔板调节到预定距离，可以减少用于发送高次谐波的通道的空间，以抑制由高次谐波产生的噪声。

公开(公告)号：US08692318B2

公开(公告)日：2014-04-08

申请号：US13104924

申请日：2011-05-10

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

摘要： A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

摘要翻译： 提供沟槽MOS结构。 沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 沟槽设置在外延层中。 栅极隔离覆盖沟槽的内壁。 沟槽栅设置在沟槽中并且具有第一导电类型。 保护环具有第二导电类型并且设置在外延层内。 加强结构具有电绝缘材料并且设置在保护环内。

公开(公告)号：US08458842B2

公开(公告)日：2013-06-11

申请号：US13104964

申请日：2011-05-10

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B08B3/02

CPC分类号： H01L21/67051 ,  H01L21/02052 ,  H01L21/67046

摘要： A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member.

摘要翻译： CMP后晶片清洗装置包括：腔室; 多个辊子，适于在所述腔室内保持和旋转晶片; 至少一个刷子，适于擦拭要清洁的晶片的表面; 以及适于将液体喷射在晶片上的液体喷射装置，所述液体喷射装置包括通过接头构件连接在一起的两个喷射杆。