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公开(公告)号:US09112144B2
公开(公告)日:2015-08-18
申请号:US13415705
申请日:2012-03-08
CPC分类号: H01L45/12 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要: A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.
摘要翻译: 制造存储单元的方法包括在基板上形成底电极,在底电极上形成可变电阻材料层,以及在可变电阻材料层上形成顶电极。 第一金属氧化物层插入顶部电极和可变电阻材料层。 在一个实施例中,第一金属氧化物层是由顶部电极的一部分的氧化提供的自形成层。 在一个实施例中,设置第二金属氧化物层,其插入第一金属氧化物层和可变电阻材料层。 第二金属氧化物可以是通过减少可变电阻材料层而形成的自形成层。
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公开(公告)号:US08154003B2
公开(公告)日:2012-04-10
申请号:US11836593
申请日:2007-08-09
IPC分类号: H01L45/00
CPC分类号: H01L45/12 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要: The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide layer provides a constant resistance.
摘要翻译: 本公开提供了一种存储单元。 存储单元包括第一电极,耦合到第一电极的可变电阻材料层,耦合可变电阻材料层的金属氧化物层; 以及耦合到所述金属氧化物层的第二电极。 在一个实施例中,金属氧化物层提供恒定的电阻。
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公开(公告)号:US20120178210A1
公开(公告)日:2012-07-12
申请号:US13415705
申请日:2012-03-08
IPC分类号: H01L21/8239
CPC分类号: H01L45/12 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要: A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.
摘要翻译: 制造存储单元的方法包括在基板上形成底电极,在底电极上形成可变电阻材料层,以及在可变电阻材料层上形成顶电极。 第一金属氧化物层插入顶部电极和可变电阻材料层。 在一个实施例中,第一金属氧化物层是由顶部电极的一部分的氧化提供的自形成层。 在一个实施例中,设置第二金属氧化物层,其插入第一金属氧化物层和可变电阻材料层。 第二金属氧化物可以是通过减少可变电阻材料层而形成的自形成层。
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公开(公告)号:US20090039332A1
公开(公告)日:2009-02-12
申请号:US11836593
申请日:2007-08-09
IPC分类号: H01L47/00
CPC分类号: H01L45/12 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要: The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide layer provides a constant resistance.
摘要翻译: 本公开提供了一种存储单元。 存储单元包括第一电极,耦合到第一电极的可变电阻材料层,耦合可变电阻材料层的金属氧化物层; 以及耦合到所述金属氧化物层的第二电极。 在一个实施例中,金属氧化物层提供恒定的电阻。
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公开(公告)号:US08618524B2
公开(公告)日:2013-12-31
申请号:US13029436
申请日:2011-02-17
申请人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
发明人: Chun-Sheng Liang , Tzyh-Cheang Lee , Fu-Liang Yang
IPC分类号: H01L45/00
CPC分类号: H01L45/12 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1683
摘要: A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.
摘要翻译: 存储器件包括相变元件,该相变元件还包括具有第一晶粒尺寸的第一相变层; 以及在所述第一相变层上的第二相变层。 第一和第二相变层是相变元件的深度区域。 第二相变层具有与第一平均晶粒尺寸不同的第二平均晶粒尺寸。
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公开(公告)号:US20100140580A1
公开(公告)日:2010-06-10
申请号:US12703571
申请日:2010-02-10
IPC分类号: H01L45/00
CPC分类号: G11C11/5678 , G11C13/0004 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.
摘要翻译: 提供了相变存储器。 该方法包括在第一电介质层中形成接触塞。 形成第二电介质层,覆盖第一电介质层和形成在其中的沟槽,暴露接触插塞的部分。 在沟槽的表面上形成金属层。 从金属层形成一个或多个加热器,使得每个加热器沿着沟槽的一个或多个侧壁形成,其中加热器沿侧壁的部分不包括相邻侧壁的拐角区域。 沟槽填充有第三电介质层,并且在第三介电层上形成第四电介质层。 在第四电介质层中形成沟槽并填充相变材料。 在相变材料上形成电极。
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公开(公告)号:US07482231B2
公开(公告)日:2009-01-27
申请号:US11529067
申请日:2006-09-28
申请人: Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人: Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号: H01L21/8239
CPC分类号: H01L29/4983 , H01L21/28282 , H01L21/823828 , H01L21/823864 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要: Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.
摘要翻译: 制造半导体芯片的方法 在基板的阵列区域上形成阵列区域栅极叠层,并且在基板的周边区域上形成周边区域栅叠层。 在衬底上沉积第一介电材料,电荷存储材料和第二介电材料。 去除第一介电材料的部分,电荷存储材料和第二介电材料,以在阵列区域栅极叠层和周边区域栅叠层上形成存储结构。 存储结构具有大致L形的横截面。 在阵列区域中形成第一源极/漏极区域。 在衬底上沉积第三介电材料和间隔物材料。 去除第三电介质材料和间隔物材料的部分以形成间隔物。 在周边区域中形成第二源极/漏极区域。
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公开(公告)号:US20080285328A1
公开(公告)日:2008-11-20
申请号:US11749017
申请日:2007-05-15
CPC分类号: G11C11/5678 , G11C13/0004 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls and a portion of the bottom of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.
摘要翻译: 提供了相变存储器。 该方法包括在第一电介质层中形成接触塞。 形成第二电介质层,覆盖第一电介质层和形成在其中的沟槽,暴露接触插塞的部分。 在沟槽的表面上形成金属层。 从金属层形成一个或多个加热器,使得每个加热器沿沟槽的一个或多个侧壁和底部的一部分形成,其中加热器沿着侧壁的部分不包括相邻侧壁的拐角区域。 沟槽填充有第三电介质层,并且在第三介电层上形成第四电介质层。 在第四电介质层中形成沟槽并填充相变材料。 在相变材料上形成电极。
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公开(公告)号:US07705424B2
公开(公告)日:2010-04-27
申请号:US11749017
申请日:2007-05-15
IPC分类号: G11C11/00
CPC分类号: G11C11/5678 , G11C13/0004 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls and a portion of the bottom of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.
摘要翻译: 提供了相变存储器。 该方法包括在第一电介质层中形成接触塞。 形成第二电介质层,覆盖第一电介质层和形成在其中的沟槽,暴露接触插塞的部分。 在沟槽的表面上形成金属层。 从金属层形成一个或多个加热器,使得每个加热器沿沟槽的一个或多个侧壁和底部的一部分形成,其中加热器沿着侧壁的部分不包括相邻侧壁的拐角区域。 沟槽填充有第三电介质层,并且在第三介电层上形成第四电介质层。 在第四电介质层中形成沟槽并填充相变材料。 在相变材料上形成电极。
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公开(公告)号:US07482236B2
公开(公告)日:2009-01-27
申请号:US11602809
申请日:2006-11-21
申请人: Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人: Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号: H01L21/8234
CPC分类号: H01L29/4983 , H01L21/28282 , H01L21/823828 , H01L21/823864 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/792 , H01L29/7923 , Y10S438/954
摘要: A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.
摘要翻译: 栅极堆叠形成在基板上。 栅极堆叠具有侧壁。 氧化物 - 氮化物 - 氧化物材料沉积在栅极叠层上。 除去氧化物 - 氮化物 - 氧化物材料的一部分以形成氧化物 - 氧化物 - 氧化物结构。 氧化物 - 氧化物 - 氧化物结构具有通常为L形的横截面,沿着栅极叠层侧壁的至少一部分和沿着衬底的水平部分具有垂直部分。 顶部氧化物材料沉积在衬底上。 在顶部氧化物材料上沉积氮化硅间隔物材料。 除去顶部氧化物材料和氮化硅间隔物材料的部分以形成通过顶部氧化物材料从氧化物 - 氮化物 - 氧化物堆叠体分离的氮化硅间隔物。 源极/漏极区域形成在衬底中。
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