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    MICROELECTROMECHANICAL SYSTEM MICROPHONE
    1.
    发明申请
    MICROELECTROMECHANICAL SYSTEM MICROPHONE 有权
    微电子系统麦克风

    公开(公告)号：US20160212551A1

    公开(公告)日：2016-07-21

    申请号：US14630620

    申请日：2015-02-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chang-Sheng Hsu ,  Yuan-Sheng Lin ,  Wei-Hua Fang ,  Kuan-Yu Wang ,  Yan-Da Chen

    IPC: H04R23/00 ,  B81B3/00

    CPC classification number: H04R23/00 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C1/00182 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003

    Abstract: A microelectromechanical system microphone includes a semiconductor-on-insulator structure, a plurality of resistors, a plurality of first openings, and a vent hole. The semiconductor-on-insulator structure includes a substrate, an insulating layer and a semiconductor layer. The resistors are formed in the semiconductor layer, the first openings are formed in the semiconductor layer, and the vent hole is formed in the insulating layer and the substrate. The resistors are connected to each other to form a resistor pattern, and the first openings are all formed within the resistor pattern.

    Abstract translation: 微机电系统麦克风包括绝缘体上半导体结构，多个电阻器，多个第一开口和通气孔。 绝缘体上半导体结构包括衬底，绝缘层和半导体层。 电阻器形成在半导体层中，第一开口形成在半导体层中，并且通气孔形成在绝缘层和基板中。 电阻器彼此连接以形成电阻器图案，并且第一开口都形成在电阻器图案内。

    Semiconductor device and method of forming the same
    4.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US08981501B2

    公开(公告)日：2015-03-17

    申请号：US13870706

    申请日：2013-04-25

    Applicant: United Microelectronics Corp.

    Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

    IPC: H01L29/84 ,  H01L21/311 ,  H01L23/48 ,  B81C1/00 ,  H01L27/06

    CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20140319693A1

    公开(公告)日：2014-10-30

    申请号：US13870706

    申请日：2013-04-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Meng-Jia Lin ,  Chang-Sheng Hsu ,  Kuo-Hsiung Huang ,  Wei-Hua Fang ,  Shou-Wei Hsieh ,  Te-Yuan Wu ,  Chia-Huei Lin

    IPC: H01L21/311 ,  H01L23/48

    CPC classification number: H01L21/31116 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0617 ,  H01L2924/0002 ,  H04R2201/003 ,  H01L2924/00

    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供了具有至少一个MOS器件，至少一个金属互连和至少一个MOS器件的衬底，该MOS器件形成在其第一表面上。 执行第一各向异性蚀刻工艺以从衬底的第二表面去除衬底的一部分，从而在衬底中形成多个通孔，其中第二表面与第一表面相对。 执行第二各向异性蚀刻工艺以从衬底的第二表面移除衬底的另一部分，从而在衬底中形成空腔，其中剩余的通孔位于腔的下方。 对空腔和剩余的通孔进行各向同性蚀刻工艺。

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