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公开(公告)号:US20100230812A1
公开(公告)日:2010-09-16
申请号:US12784806
申请日:2010-05-21
申请人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
发明人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
IPC分类号: H01L23/485
CPC分类号: H01L24/12 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0231 , H01L2224/0401 , H01L2224/05599 , H01L2224/1132 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/3011 , H01L2924/351
摘要: A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.
摘要翻译: 公开了一种微电子组件,其包括具有触点的半导体晶片,覆盖半导体晶片的第一表面的电介质材料的柔性突起,以及覆盖半导体晶片的第一表面和顺应凸块的边缘的电介质层。 顺应性凸块具有可通过电介质层访问的平面顶表面。 导电迹线可以与触点电连接并从其延伸以覆盖顺应性凸块的平坦顶表面。 导电元件可以覆盖与导电迹线接触的平面顶表面。
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公开(公告)号:US20120091582A1
公开(公告)日:2012-04-19
申请号:US13335022
申请日:2011-12-22
申请人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
发明人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
IPC分类号: H01L23/498
CPC分类号: H01L24/12 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0231 , H01L2224/0401 , H01L2224/05599 , H01L2224/1132 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/3011 , H01L2924/351
摘要: A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.
摘要翻译: 公开了一种微电子组件,其包括具有触点的半导体晶片,覆盖半导体晶片的第一表面的电介质材料的柔性突起,以及覆盖半导体晶片的第一表面和顺应凸块的边缘的电介质层。 顺应性凸块具有可通过电介质层访问的平面顶表面。 导电迹线可以与触点电连接并从其延伸以覆盖顺应性凸块的平坦顶表面。 导电元件可以覆盖与导电迹线接触的平面顶表面。
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公开(公告)号:US08115308B2
公开(公告)日:2012-02-14
申请号:US12784806
申请日:2010-05-21
申请人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
发明人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
IPC分类号: H01L23/28
CPC分类号: H01L24/12 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0231 , H01L2224/0401 , H01L2224/05599 , H01L2224/1132 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/3011 , H01L2924/351
摘要: A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.
摘要翻译: 公开了一种微电子组件,其包括具有触点的半导体晶片,覆盖半导体晶片的第一表面的电介质材料的柔性突起,以及覆盖半导体晶片的第一表面和顺应凸块的边缘的电介质层。 顺应性凸块具有可通过电介质层访问的平面顶表面。 导电迹线可以与触点电连接并从其延伸以覆盖顺应性凸块的平坦顶表面。 导电元件可以覆盖与导电迹线接触的平面顶表面。
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公开(公告)号:US08759973B2
公开(公告)日:2014-06-24
申请号:US13335022
申请日:2011-12-22
申请人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
发明人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
IPC分类号: H01L23/48
CPC分类号: H01L24/12 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0231 , H01L2224/0401 , H01L2224/05599 , H01L2224/1132 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/3011 , H01L2924/351
摘要: A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.
摘要翻译: 公开了一种微电子组件,其包括具有触点的半导体晶片,覆盖半导体晶片的第一表面的电介质材料的柔性突起,以及覆盖半导体晶片的第一表面和顺应凸块的边缘的电介质层。 顺应性凸块具有可通过电介质层访问的平面顶表面。 导电迹线可以与触点电连接并从其延伸以覆盖顺应性凸块的平坦顶表面。 导电元件可以覆盖与导电迹线接触的平面顶表面。
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公开(公告)号:US07749886B2
公开(公告)日:2010-07-06
申请号:US11643021
申请日:2006-12-20
申请人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
发明人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
IPC分类号: H01L21/44
CPC分类号: H01L24/12 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0231 , H01L2224/0401 , H01L2224/05599 , H01L2224/1132 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/3011 , H01L2924/351
摘要: A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.
摘要翻译: 制造微电子组件的方法包括提供具有可在第一表面处接触的触点的半导体晶片,在第一表面上形成顺应性凸块并在顺应性凸块上沉积牺牲层。 该方法包括研磨牺牲层和顺应性凸块,以平坦化顺应凸块的顶表面,由此平坦化的顶表面可通过所述牺牲层进入。 去除牺牲层以暴露顺应性凸块和触点。 将硅树脂层沉积在顺应性凸块上,并且除去硅氧烷层的部分以露出可在半导体晶片的第一表面处接触的触点。 导电迹线形成为具有与触点电连接的第一端和覆盖顺应凸块的第二端,并且导电元件设置在迹线的第二端的顶部。
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公开(公告)号:US20080150121A1
公开(公告)日:2008-06-26
申请号:US11643021
申请日:2006-12-20
申请人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
发明人: Vage Oganesian , Guilian Gao , Belgacem Haba , David Ovrutsky
CPC分类号: H01L24/12 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0231 , H01L2224/0401 , H01L2224/05599 , H01L2224/1132 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/3011 , H01L2924/351
摘要: A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.
摘要翻译: 制造微电子组件的方法包括提供具有可在第一表面处接触的触点的半导体晶片,在第一表面上形成顺应性凸块并在顺应性凸块上沉积牺牲层。 该方法包括研磨牺牲层和顺应性凸块,以平坦化顺应凸块的顶表面,由此平坦化的顶表面可通过所述牺牲层进入。 去除牺牲层以暴露顺应性凸块和触点。 将硅树脂层沉积在顺应性凸块上,并且除去硅氧烷层的部分以露出可在半导体晶片的第一表面处接触的触点。 导电迹线形成为具有与触点电连接的第一端和覆盖顺应凸块的第二端,并且导电元件设置在迹线的第二端的顶部。
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公开(公告)号:US08053281B2
公开(公告)日:2011-11-08
申请号:US12315855
申请日:2008-12-04
IPC分类号: H01L21/00
CPC分类号: H01L23/13 , H01L21/4853 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/4824 , H01L2224/4911 , H01L2224/49174 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/19107 , H01L2224/45099 , H01L2224/05599
摘要: A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.
摘要翻译: 提供了一种用于在晶片级形成微电子封装的方法。 这种方法可以包括提供具有其上具有电触点图案的表面的半导体晶片。 可以提供具有结合到导电层的柔性介电层的插入件部件。 可以通过柔性电介质层和对应于电接触图案的导电层形成孔的图案。 柔性电介质层可以与半导体晶片表面接触,使得孔的图案与接触图案在对准位置中,并且柔性介电层和半导体晶片表面然后在对准位置接合以使半导体晶片和 所述插入器部件形成晶片级半导体封装。 可以对晶片级半导体封装进行切割以形成单独的半导体芯片封装。
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公开(公告)号:US20090162975A1
公开(公告)日:2009-06-25
申请号:US12315855
申请日:2008-12-04
IPC分类号: H01L21/00
CPC分类号: H01L23/13 , H01L21/4853 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/4824 , H01L2224/4911 , H01L2224/49174 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/19107 , H01L2224/45099 , H01L2224/05599
摘要: A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.
摘要翻译: 提供了一种用于在晶片级形成微电子封装的方法。 这种方法可以包括提供具有其上具有电触点图案的表面的半导体晶片。 可以提供具有结合到导电层的柔性介电层的插入件部件。 可以通过柔性电介质层和对应于电接触图案的导电层形成孔的图案。 柔性电介质层可以与半导体晶片表面接触,使得孔的图案与触点图案在对准位置中,并且柔性电介质层和半导体晶片表面然后在对准位置接合以使半导体晶片和 所述插入器部件形成晶片级半导体封装。 可以对晶片级半导体封装进行切割以形成单独的半导体芯片封装。
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公开(公告)号:US07719121B2
公开(公告)日:2010-05-18
申请号:US11581888
申请日:2006-10-17
申请人: Giles Humpston , Guilian Gao , Belgacem Haba
发明人: Giles Humpston , Guilian Gao , Belgacem Haba
IPC分类号: H01L23/48
CPC分类号: H01L23/4985 , H01L23/49811 , H01L24/48 , H01L2224/45014 , H01L2224/48091 , H01L2924/00014 , H01L2924/3011 , H01L2224/45015 , H01L2924/207
摘要: A microelectronic package includes a microelectronic element having contacts, a flexible substrate spaced from and overlying the microelectronic element and a plurality of conductive posts extending from the flexible substrate and projecting away from the microelectronic element. The conductive posts are electrically interconnected with the microelectronic element. Each conductive post has a conductive base that is in contact with the flexible substrate and a conductive tip that extends from the base, with the base of the conductive post having a larger diameter than the tip of the conductive post. In certain embodiments, the conductive base and the conductive tip have a cylindrical shape.
摘要翻译: 微电子封装包括具有触点的微电子元件,与微电子元件隔开并覆盖的柔性基板以及从柔性基板延伸并远离微电子元件突出的多个导电柱。 导电柱与微电子元件电互连。 每个导电柱具有与柔性基板接触的导电基底和从基部延伸的导电尖端,导电柱的基部具有比导电柱的尖端更大的直径。 在某些实施例中,导电基底和导电尖端具有圆柱形形状。
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公开(公告)号:US08378487B2
公开(公告)日:2013-02-19
申请号:US13356752
申请日:2012-01-24
申请人: Teck-Gyu Kang , Belgacem Haba , Guilian Gao
发明人: Teck-Gyu Kang , Belgacem Haba , Guilian Gao
IPC分类号: H01L21/44
CPC分类号: H01L24/16 , H01L21/4853 , H01L23/3114 , H01L23/49811 , H01L24/02 , H01L24/11 , H01L24/12 , H01L24/81 , H01L2224/02125 , H01L2224/0231 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/11334 , H01L2224/13023 , H01L2224/13099 , H01L2224/16 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/19042 , H01L2224/29099
摘要: Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.
摘要翻译: 公开了包括具有倾斜侧壁的立管和制造这种芯片封装的方法的晶片级芯片封装。 本发明的晶片级芯片封装可有利地用于各种微电子组件中。
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