公开(公告)号：US20050191948A1

公开(公告)日：2005-09-01

申请号：US11112104

申请日：2005-04-22

申请人： Vishnu Agarwal ,  Scott Meikle

发明人： Vishnu Agarwal ,  Scott Meikle

IPC分类号： B24B37/22 ,  B24B37/26 ,  B24D3/22 ,  B24D13/14 ,  B24B1/00

CPC分类号： B24B37/26 ,  B24B37/22 ,  B24D3/22 ,  Y10S977/776 ,  Y10S977/883 ,  Y10S977/888

摘要： Polishing pads used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such polishing pads. In one aspect of the invention, a polishing pad for planarizing microelectronic-device substrate assemblies has a backing member including a first surface and a second surface, a plurality of pattern elements distributed over the first surface of the backing member, and a hard cover layer over the pattern elements. The pattern elements define a plurality of contour surfaces projecting away from the first surface of the backing member. The cover layer at least substantially conforms to the contour surfaces of the pattern elements to form a plurality of hard nodules projecting away from the first surface of the backing member. The hard nodules define abrasive elements to contact and abrade material from a microelectronic-device substrate assembly. As such, the cover layer defines at least a portion of a planarizing surface of the polishing pad.

摘要翻译： 用于制造微电子器件的抛光垫，以及用于制造和使用这种抛光垫的装置和方法。 在本发明的一个方面，用于平坦化微电子器件衬底组件的抛光垫具有包括第一表面和第二表面的背衬构件，分布在衬垫构件的第一表面上的多个图案元件和硬覆盖层 超过图案元素。 图案元件限定远离背衬构件的第一表面突出的多个轮廓表面。 覆盖层至少基本上符合图案元件的轮廓表面，以形成多个突出远离背衬构件的第一表面的硬结节。 硬结节定义研磨元件以接触和研磨来自微电子器件衬底组件的材料。 因此，覆盖层限定抛光垫的平坦化表面的至少一部分。

公开(公告)号：US07535047B2

公开(公告)日：2009-05-19

申请号：US10922582

申请日：2004-08-20

申请人： Vishnu Agarwal ,  Garry Anthony Mercaldi

发明人： Vishnu Agarwal ,  Garry Anthony Mercaldi

IPC分类号： H01L29/94

CPC分类号： H01L21/28202 ,  C23C8/02 ,  C23C16/56 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02263 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28176 ,  H01L21/28238 ,  H01L21/3125 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

摘要： An ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

摘要翻译： 公开了一种半导体器件上的超薄介电膜或电介质层。 在一个实施例中，在衬底上形成氧化物层。 在氧化物层上沉积含硅材料。 将沉积的材料和氧化物层在等离子体中进行处理以形成电介质层或超薄电介质膜。 含硅介电层可以允许改进或更小的半导体器件。 含硅介电层可以在低温下制造。 改进的或更小的半导体器件可以通过减少泄漏，增加介电常数或在较低温度下制造来实现。

公开(公告)号：US06821838B2

公开(公告)日：2004-11-23

申请号：US10273666

申请日：2002-10-18

申请人： Vishnu Agarwal ,  Garry Anthony Mercaldi

发明人： Vishnu Agarwal ,  Garry Anthony Mercaldi

IPC分类号： H01L2100

CPC分类号： H01L21/28202 ,  C23C8/02 ,  C23C16/56 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02263 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28176 ,  H01L21/28238 ,  H01L21/3125 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

摘要： A method of forming an ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment of the present invention, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

摘要翻译： 公开了一种在半导体器件上形成超薄电介质膜或电介质层的方法。 在本发明的一个实施例中，在衬底上形成氧化物层。 在氧化物层上沉积含硅材料。 将沉积的材料和氧化物层在等离子体中进行处理以形成电介质层或超薄电介质膜。 含硅介电层可以允许改进或更小的半导体器件。 含硅介电层可以在低温下制造。 改进的或更小的半导体器件可以通过减少泄漏，增加介电常数或在较低温度下制造来实现。

公开(公告)号：US20080019634A1

公开(公告)日：2008-01-24

申请号：US11903678

申请日：2007-09-24

申请人： Vishnu Agarwal

发明人： Vishnu Agarwal

IPC分类号： G02B6/12

CPC分类号： G02B6/12002 ,  G02B6/12004 ,  G02B6/12007 ,  G02B6/30 ,  H01S3/06758

摘要： The present technique relates to a device including an optical integrated circuit amplifier and another type of optical integrated circuit. The optical integrated circuit amplifiers and other optical integrated circuits are coupled together through optical paths. The optical integrated circuit amplifiers and other optical integrated circuits of the optical components are fabricated on the same substrate. The optical integrated circuit amplifiers and other optical integrated circuit amplifiers maybe fabricated on different levels of the same substrate.

摘要翻译： 本技术涉及包括光学集成电路放大器和另一种类型的光学集成电路的器件。 光学集成电路放大器和其他光学集成电路通过光路耦合在一起。 光学组件的光学集成电路放大器和其他光学集成电路被制造在相同的衬底上。 光学集成电路放大器和其他光学集成电路放大器可以在相同衬底的不同级别上制造。

公开(公告)号：US20060234465A1

公开(公告)日：2006-10-19

申请号：US11452816

申请日：2006-06-13

申请人： Vishnu Agarwal ,  Gurtej Sandhu

发明人： Vishnu Agarwal ,  Gurtej Sandhu

IPC分类号： H01L21/44

CPC分类号： H01L28/75 ,  C23C16/34 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76868 ,  H01L21/7687 ,  H01L27/1085 ,  H01L28/55 ,  H01L2221/1078

摘要： In one aspect, the invention includes a method of forming a material comprising tungsten and nitrogen, comprising: a) providing a substrate; b) depositing a layer comprising tungsten and nitrogen over the substrate; and c) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma. In another aspect, the invention includes a method of forming a capacitor, comprising: a) forming a first electrical node; b) forming a dielectric layer over the first electrical node; c) forming a second electrical node; and d) providing a layer comprising tungsten and nitrogen between the dielectric layer and one of the electrical nodes, the providing comprising; i) depositing a layer comprising tungsten and nitrogen; and ii) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma.

公开(公告)号：US20050266773A1

公开(公告)日：2005-12-01

申请号：US11197287

申请日：2005-08-03

申请人： Vishnu Agarwal

发明人： Vishnu Agarwal

IPC分类号： B24B21/04 ,  B24B37/04 ,  B24B49/12 ,  B24D7/12 ,  B24B49/00

CPC分类号： B24B37/26 ,  B24B21/04 ,  B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  B24D7/12

摘要： Planarizing machines, planarizing pads, and methods for planarizing or endpointing mechanical and/or chemical-mechanical planarization of microelectronic substrates. One particular embodiment is a planarizing machine that controls the movement of a planarizing pad along a pad travel path to provide optical analysis of a substrate assembly during a planarizing cycle. The planarizing machine can include a table having an optical opening at an illumination site in a planarizing zone and a light source aligned with the illumination site to direct a light beam through the optical opening in the table. The planarizing machine can further include a planarizing pad and a pad advancing mechanism. The planarizing pad has a planarizing medium and at least one optically transmissive window along the pad travel path. The pad advancing mechanism has an actuator system coupled to the pad and a position monitor coupled to the actuator system. The actuator system is configured to move the planarizing pad over the table along the pad travel path, and the position monitor is configured to sense the position of a window in the planarizing pad relative to the opening in the table at the illumination site.

摘要翻译： 平面化机器，平面化焊盘和用于平面化或终点微电子衬底的机械和/或化学机械平面化的方法。 一个特定实施例是一种平面化机器，其控制平坦化焊盘沿焊盘移动路径的运动，以在平坦化循环期间提供衬底组件的光学分析。 平面化机器可以包括具有在平坦化区域中的照明位置处的光学开口的台面和与照明位置对准的光源以将光束引导通过桌子中的光学开口。 平面化机还可以包括平坦化垫和垫推进机构。 平坦化焊盘具有平坦化介质和沿着焊盘移动路径的至少一个光学透射窗口。 垫前进机构具有耦合到衬垫的致动器系统和耦合到致动器系统的位置监视器。 所述致动器系统被配置为沿所述垫移动路径将所述平坦化垫移动到所述工作台上，并且所述位置监视器构造成相对于所述照明位置处的所述台中的开口感测所述平坦化垫中的窗口的位置。

公开(公告)号：US20050164481A1

公开(公告)日：2005-07-28

申请号：US11088311

申请日：2005-03-23

申请人： Scott Deboer ,  Vishnu Agarwal

发明人： Scott Deboer ,  Vishnu Agarwal

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L27/10855 ,  H01L21/76895 ,  H01L23/5283 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

公开(公告)号：US20070007572A1

公开(公告)日：2007-01-11

申请号：US11517680

申请日：2006-09-08

申请人： Vishnu Agarwal ,  Garry Mercaldi

发明人： Vishnu Agarwal ,  Garry Mercaldi

IPC分类号： H01L21/8242 ,  H01L29/94 ,  H01L21/331

CPC分类号： H01L28/55 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/964

摘要： A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

公开(公告)号：US20060245682A1

公开(公告)日：2006-11-02

申请号：US11454692

申请日：2006-06-16

申请人： Vishnu Agarwal

发明人： Vishnu Agarwal

IPC分类号： G02B6/12

CPC分类号： G02B6/12002 ,  G02B6/12004 ,  G02B6/12007 ,  G02B6/30 ,  H01S3/06758

摘要： The present technique relates to a method for fabricating an optical integrated circuit amplifier with another type of optical integrated circuit. In optical networks, optical components exchange optical signals to communicate between different systems coupled to the optical components. The optical components may include optical integrated circuit amplifiers and other optical integrated circuits coupled together through optical paths. The optical integrated circuit amplifiers and other optical integrated circuits of the optical components are fabricated on the same substrate to reduce the cost of fabrication, maintenance and installation, while enhancing the performance of the optical component.

摘要翻译： 本技术涉及一种用于制造具有另一类型的光集成电路的光集成电路放大器的方法。 在光网络中，光学部件交换光信号以在耦合到光学部件的不同系统之间进行通信。 光学部件可以包括通过光路耦合在一起的光学集成电路放大器和其它光学集成电路。 光学部件的光学集成电路放大器和其他光学集成电路被制造在相同的基板上，以降低制造，维护和安装的成本，同时提高光学部件的性能。

公开(公告)号：US20060180844A1

公开(公告)日：2006-08-17

申请号：US11361111

申请日：2006-02-24

申请人： Vishnu Agarwal

发明人： Vishnu Agarwal

IPC分类号： H01L29/94

CPC分类号： H01L21/02183 ,  H01L21/022 ,  H01L21/02337 ,  H01L21/02356 ,  H01L27/1085 ,  H01L28/55

摘要： The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received therebetween. The high K capacitor dielectric region has a high K substantially amorphous material layer and a high K substantially crystalline material layer. In one implementation, a capacitor forming method includes forming a first capacitor electrode layer over a substrate. A substantially amorphous first high K capacitor dielectric material layer is deposited over the first capacitor electrode layer. The substantially amorphous high K first capacitor dielectric material layer is converted to be substantially crystalline. After the converting, a substantially amorphous second high K capacitor dielectric material layer is deposited over the substantially crystalline first high K capacitor dielectric material layer. A second capacitor electrode layer is formed over the substantially amorphous second high K capacitor dielectric material layer.

摘要翻译： 本发明包括集成电路和形成电容器的方法。 在一个实施方式中，集成电路包括具有第一电容器电极，第二电容器电极和接收在其间的高K电容器电介质区域的电容器。 高K电容电介质区域具有高K基本无定形材料层和高K基本结晶材料层。 在一个实施方式中，电容器形成方法包括在衬底上形成第一电容器电极层。 在第一电容器电极层上沉积基本无定形的第一高K电容介电材料层。 基本无定形的高K第一电容器介电材料层被转换成基本上是结晶的。 在转换之后，在基本上晶体的第一高K电容介电材料层上沉积基本非晶的第二高K电容器介电材料层。 第二电容器电极层形成在基本无定形的第二高K电容电介质材料层上。