公开(公告)号：US5466954A

公开(公告)日：1995-11-14

申请号：US360486

申请日：1994-12-21

Applicant: Jose J. Aizpuru ,  Walter T. Matzen

Inventor： Jose J. Aizpuru ,  Walter T. Matzen

IPC: H01L31/11 ,  H01L27/14 ,  H01L31/00

CPC classification number: H01L31/1105 ,  Y10T307/773

Abstract: A phototransistor is provided with a first resistor that operates as a shunt and a second resistor that operates to protect the device from damage that could be caused by a reverse bias condition. The possible damage results from the creation of a PN junction relationship caused by the doping of N conductivity type material with P.sup.+ conductivity type material in order to form the first resistor. This junction relationship creates a parasitic diode that provides a current path between the emitter and collector terminals of the phototransistor. In order to prevent damage that might occur during a reverse voltage connection, a second resistor is connected between the emitter of transistor Q.sub.1 and the first resistor. The second resistor is in series with the junction relationship resulting from the structure used to form the first resistor and therefore serves to limit the current flowing between the emitter and collector terminals of the transistor under reversed bias conditions.

Abstract translation: 光电晶体管设置有作为分流器操作的第一电阻器和用于保护器件免受可能由反向偏置条件引起的损坏的第二电阻器。 可能的损害是由于由P导电型材料掺杂N导电型材料引起的PN结关系产生的，从而形成第一电阻。 该结关系产生寄生二极管，其提供光电晶体管的发射极和集电极端之间的电流路径。 为了防止在反向电压连接期间可能发生的损坏，第二电阻连接在晶体管Q1的发射极和第一电阻之间。 第二电阻器与由用于形成第一电阻器的结构产生的结关系串联，因此用于限制在反向偏置条件下在晶体管的发射极和集电极端子之间流动的电流。

公开(公告)号：US3936789A

公开(公告)日：1976-02-03

申请号：US475712

申请日：1974-06-03

Applicant: Walter T. Matzen ,  Don L. Kendall

Inventor： Walter T. Matzen ,  Don L. Kendall

IPC: H01C17/232 ,  H01C7/04

CPC classification number: H01C17/232

Abstract: A spreading-resistance silicon thermistor having high-precision values of resistance and temperature coefficient of resistance (TCR) is produced by a high-volume, low-cost, photolithographic technique, wherein multiple thin-film contacts are tested and selectively trimmed to permit computerized control of precision resistance values in a production-line operation.

Abstract translation: 具有高精度电阻和温度系数值（TCR）的扩展电阻硅热敏电阻是通过高容量，低成本的光刻技术产生的，其中测试多个薄膜触点并选择性地修整以允许计算机化 在生产线操作中控制精密电阻值。

公开(公告)号：US5130760A

公开(公告)日：1992-07-14

申请号：US714113

申请日：1991-06-11

Applicant: Walter T. Matzen ,  Ronald B. Foster

Inventor： Walter T. Matzen ,  Ronald B. Foster

IPC: H01L29/866 ,  H01L27/02

CPC classification number: H01L27/0248 ,  Y10S257/926

Abstract: A semiconductor device is provided for use as a bidirectional surge suppressor circuit. It incorporates doped regions of substrate and epitaxial layers which result in a dual Zener diode arrangement having the Zener diodes associated in an opposite polarity arrangement. The semiconductor device comprises a substrate with an epitaxial layer deposited on one of its surfaces. In an upper surface of the epitaxial layer, first and second regions of P type material are diffused with guard rings comprising P+ type material diffused around the first and second regions. The guard rings are heavily doped and extend much deeper than the relatively shallow junctions of P material. A channel stopper of N+ conductivity type material is diffused into the upper surface of the epitaxial layer to provide a channel stopper, or sinker, around both the first and second regions and their associated guard rings and, additionally, between the first and second regions. This structure provides several significant advantages including reduced current leakage reliability, uniform breakdown voltage, crack resistance and a smaller area needed to provide the required thermal capacity.

公开(公告)号：US3982266A

公开(公告)日：1976-09-21

申请号：US530774

申请日：1974-12-09

Applicant: Walter T. Matzen ,  Wilton L. Workman

Inventor： Walter T. Matzen ,  Wilton L. Workman

IPC: H01L21/8226 ,  H01L27/02 ,  H01L27/082 ,  H01L29/06 ,  H01L29/732 ,  H03K19/091 ,  H01L27/04

CPC classification number: H01L27/0233 ,  H01L21/8226 ,  H01L27/0821 ,  H01L29/0649 ,  H01L29/7327 ,  H03K19/091 ,  Y10S148/098 ,  Y10S148/117 ,  Y10S148/136

Abstract: An integrated injection logic (IIL) structure including active devices, one of which is a switching transistor having base current injection from another active device where an epitaxial zone forms an emitter-base junction. A diffused zone in the epitaxial layer forms a collector for the switching transistor and an insulating structure defines perimeters of the collector-base junction and the emitter-base junction such that the widths thereof are about equal for maximizing current gain with minimal temperature dependence.

Abstract translation: 包括有源器件的集成注入逻辑（IIL）结构，其中一个是具有来自另一个有源器件的基极电流注入的开关晶体管，其中外延区形成发射极 - 基极结。 外延层中的扩散区形成用于开关晶体管的集电极，并且绝缘结构限定集电极 - 基极结和发射极 - 基极结的周长，使得其宽度大致相等，以便以最小的温度依赖性最大化电流增益。

公开(公告)号：US06492697B1

公开(公告)日：2002-12-10

申请号：US09542213

申请日：2000-04-04

Applicant: Mark R. Plagens ,  Michael J. Haji-Sheikh ,  Walter T. Matzen

Inventor： Mark R. Plagens ,  Michael J. Haji-Sheikh ,  Walter T. Matzen

IPC: H01L2982

CPC classification number: H01L43/065 ,  G01R33/07

Abstract: A Hall-effect element includes an isolating layer and an active layer of a first electrical conductivity type disposed on the isolating layer, the active layer having a surface. A first set of contacts is disposed in contact with the surface along a first axis, and a second set of contacts is disposed in contact with the surface along a second axis transverse to the first axis. An insulating layer is disposed on the surface. A metal control field plate is disposed on the insulating layer and is coupleable to a voltage source to control the accumulation of charge carriers at the surface of the active layer to vary the resistance of the active layer. Also, a method is provided for reducing null offset in a Hall-effect element. The method includes the steps of providing an isolating layer, disposing an active layer of a first electrical conductivity type on the isolating layer, the active layer having a surface, disposing a first set of contacts on the surface along a first axis, disposing a second set of contacts on the surface along a second axis transverse to the first axis; and disposing an insulating layer on the surface. A voltage is applied across the insulating layer to control the accumulation of charge carriers at the surface to vary the resistance of the active layer.

Abstract translation: 霍尔效应元件包括隔离层和布置在隔离层上的第一导电类型的有源层，活性层具有表面。 第一组触点设置成沿着第一轴线与表面接触，并且第二组触点设置成沿着横向于第一轴线的第二轴线与表面接触。 绝缘层设置在表面上。 金属控制场板设置在绝缘层上并且可耦合到电压源以控制在有源层的表面上的载流子的累积以改变有源层的电阻。 此外，提供了一种用于减少霍尔效应元素中的零偏移的方法。 该方法包括以下步骤：提供隔离层，在隔离层上设置第一导电类型的有源层，有源层具有表面，沿着第一轴在表面上设置第一组触点， 沿着横向于第一轴线的第二轴线的表面上的一组触点; 并在表面上设置绝缘层。 在绝缘层上施加电压以控制表面处的电荷载流子的累积以改变有源层的电阻。

公开(公告)号：US3962713A

公开(公告)日：1976-06-08

申请号：US409509

申请日：1973-10-25

Applicant: Don L. Kendall ,  Walter T. Matzen

Inventor： Don L. Kendall ,  Walter T. Matzen

IPC: H01L21/00 ,  H01L23/29 ,  H01L27/00 ,  H01L29/00 ,  H01L29/93 ,  H01L29/94

CPC classification number: H01L29/945 ,  H01L21/00 ,  H01L23/291 ,  H01L27/00 ,  H01L29/00 ,  H01L29/93 ,  H01L2224/4846 ,  H01L2224/4847 ,  H01L2924/12032

Abstract: Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate and utilizing the sidewalls of the grooves as surface. A thin layer of dielectric is formed over the increased surface area, and thereafter a metal layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may be formed instead of a dielectric capacitor by forming a P-N junction comprising the increased surface area, and thereover forming the metallized contact.

Abstract translation: 公开了一种半导体电容器，其利用其形成的半导体衬底的体积来产生增加的表面积，从而提供增加的电容。 通过在半导体衬底的表面中形成选择性间隔的沟槽并且利用沟槽的侧壁作为表面来增加表面积。 在增加的表面积上形成薄的电介质层，然后在电介质层上形成金属层以提供介质电容器。 可以通过形成包括增加的表面积的P-N结，并且形成金属化接触，来代替介电电容器来形成有源结P-N电容器。

公开(公告)号：US6069905A

公开(公告)日：2000-05-30

申请号：US1894

申请日：1997-12-31

Applicant: Richard A Davis ,  Walter T. Matzen ,  James K. Guenter ,  David Smith

Inventor： Richard A Davis ,  Walter T. Matzen ,  James K. Guenter ,  David Smith

IPC: G02B6/42 ,  H01S3/00 ,  H01S5/00 ,  H01S5/022 ,  H01S5/026 ,  H01S5/183 ,  H01S3/18

CPC classification number: H01S5/02296 ,  G02B6/4204 ,  H01S5/02284 ,  H01S5/0264 ,  H01S5/0683 ,  H01S5/183

Abstract: A vertical cavity surface emitting laser having intensity control for maintaining a constant proportional output under varying conditions of the laser. A tilted window is situated over the laser output to reflect a portion of the light to a photo detector area. Signals representing light on the photo detector go to a feedback circuit which controls the power output of the laser. The tilted window has a metallic coating for partial reflection and for minimizing polarization effects on reflected and transmitted light. The photo detector has an anti-reflective coating for likewise minimizing polarization effects of the detected light. The VCSEL and photo detector are situated on the same substrate.

Abstract translation: 具有强度控制的垂直腔表面发射激光器，用于在激光器的变化条件下保持恒定的比例输出。 倾斜的窗口位于激光输出端上，以将一部分光反射到光电检测器区域。 表示光检测器上的光的信号转到控制激光器功率输出的反馈电路。 倾斜的窗口具有用于部分反射的金属涂层并且用于使对反射和透射光的偏振效应最小化。 光电检测器具有防反射涂层，用于同样使检测到的光的偏振效应最小化。 VCSEL和光电检测器位于同一基板上。

公开(公告)号：US4131983A

公开(公告)日：1979-01-02

申请号：US758387

申请日：1977-01-10

Applicant: Walter T. Matzen

Inventor： Walter T. Matzen

IPC: H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  B01J17/00

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/7886 ,  Y10S148/136

Abstract: A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

Abstract translation: 已经制造了双注入器，浮栅MOS非易失性半导体存储器件（DIFMOS），其中电子注入装置包括通过离子注入控制的具有临界掺杂剂浓度的p + n +结。 接点被雪崩以在浮动栅极上“写入”一个电荷，并且空穴注入器结（n + / p-）被雪崩以“擦除”电荷。 其栅极是浮动栅极的延伸的MOS感测晶体管“读取”在浮动栅极上存在或不存在电荷。 在优选实施例中，空穴注入装置包括用于将电压偏压耦合到浮动栅极的MOS“自举”电容器。

公开(公告)号：US4017885A

公开(公告)日：1977-04-12

申请号：US532334

申请日：1974-12-13

Applicant: Don L. Kendall ,  Walter T. Matzen

Inventor： Don L. Kendall ,  Walter T. Matzen

IPC: H01L27/06 ,  H01L27/08 ,  H01L29/04 ,  H01L29/06 ,  H01L29/93 ,  H01L29/94 ,  H01L27/04 ,  H01L29/92

CPC classification number: H01L29/945 ,  H01L27/0647 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/93 ,  H01L2224/4846 ,  Y10S148/051 ,  Y10S148/115 ,  Y10S148/136

Abstract: Disclosed is a semiconductor capacitor which utilizes the volume of the semiconductor substrate in which it is formed to create increased surface area and thereby to provide increased capacitance. The surface area is increased by forming selectively spaced grooves in the surface of the semiconductor substrate by orientation dependent etches and utilizing the sidewalls of the grooves as surface. Groove depth is limited to a predetermined value by etching time, geometrical constraints, or by etch stops. This provides for precise control of capacitance values on a batch or commercial basis. Increases up to at least 100-fold in capacitance as compared to a flat capacitor structure as possible. A thin layer of dielectric is formed over the increased surface area, and thereafter a conducting layer is formed over the dielectric layer to provide a dielectric capacitor. An active junction P-N capacitor may also be formed.

Abstract translation: 公开了一种半导体电容器，其利用其形成的半导体衬底的体积来产生增加的表面积，从而提供增加的电容。 通过在半导体衬底的表面中通过取向依赖的蚀刻形成选择性间隔的沟槽并且利用沟槽的侧壁作为表面来增加表面积。 通过蚀刻时间，几何约束或通过蚀刻停止将槽深度限制在预定值。 这提供了批量或商业基础上的电容值的精确控制。 与平坦的电容器结构相比，电容可以增加至少100倍。 在增加的表面积上形成薄的电介质层，然后在电介质层上形成导电层以提供介质电容器。 还可以形成有源结P-N电容器。