公开(公告)号：US5891784A

公开(公告)日：1999-04-06

申请号：US430084

申请日：1995-04-27

申请人： Wan Yee Cheung ,  Sailesh Chittipeddi ,  Chong-Cheng Fu ,  Taeho Kook ,  Avinoam Kornblit ,  Steven Alan Lytle ,  Kurt George Steiner ,  Tungsheng Yang

发明人： Wan Yee Cheung ,  Sailesh Chittipeddi ,  Chong-Cheng Fu ,  Taeho Kook ,  Avinoam Kornblit ,  Steven Alan Lytle ,  Kurt George Steiner ,  Tungsheng Yang

IPC分类号： H01L21/027 ,  H01L21/336 ,  H01L21/331

CPC分类号： H01L21/0276 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  Y10S438/952

摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.

摘要翻译： 公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。 使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。 抗反射涂层有助于防止反光门开槽。 可以形成各种硅化和非硅化的结构。

公开(公告)号：US06879046B2

公开(公告)日：2005-04-12

申请号：US10038371

申请日：2002-01-02

申请人： Gerald W Gibson, Jr. ,  Scott Jessen ,  Steven Alan Lytle ,  Kurt George Steiner ,  Susan Clay Vitkavage

发明人： Gerald W Gibson, Jr. ,  Scott Jessen ,  Steven Alan Lytle ,  Kurt George Steiner ,  Susan Clay Vitkavage

IPC分类号： H01L23/522 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L59/40

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/312 ,  H01L21/3146 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N—H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide. The hardmask and etch-stop layer enable the formation of a dual-damascene opening in the film stack, and the film structure of the present invention precludes N—H base groups from diffusing from the low-k dielectric films and neutralizing acid catalysts in the photoresist used to define the dual damascene opening.

摘要翻译： 分裂阻挡层使得铜互连线可以与低k电介质膜结合使用，方法是防止N-H基团扩散到光致抗蚀剂中，从而使光致抗蚀剂不可溶。 分裂阻挡层设置在铜和低k电介质之间，并且包括与铜接触的含氮的无氧膜和与低k电介质膜接触的含氧无氮膜。 含氮膜防止形成不期望的铜氧化物，并且含氧膜防止N-H基团扩散到低k电介质膜中。 在示例性实施例中，含氧膜可以是氧掺杂碳化硅膜。 在另一个实施例中，低k电介质膜的薄膜叠层包括蚀刻停止层和各自由氧掺杂的碳化硅形成的硬掩模。 硬掩模和蚀刻停止层使得能够在膜堆叠中形成双镶嵌开口，并且本发明的膜结构排除了NH基团从所使用的光致抗蚀剂中的低k电介质膜和中和酸催化剂扩散 定义双镶嵌开口。

公开(公告)号：US06362638B1

公开(公告)日：2002-03-26

申请号：US09388203

申请日：1999-09-01

申请人： Robert Alan Ashton ,  Steven Alan Lytle ,  Mary Drummond Roby ,  Daniel Joseph Vitkavage

发明人： Robert Alan Ashton ,  Steven Alan Lytle ,  Mary Drummond Roby ,  Daniel Joseph Vitkavage

IPC分类号： G01R3126

CPC分类号： G01R31/04

摘要： A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.

摘要翻译： 提供了一种用于测量集成电路互连中的开尔文接触电阻的方法和装置，具有覆盖通过测量的通孔和互连的上开和下开口接触电阻触点，以及基本上位于上开和下开口触点之间的第三导体，以及 与通道接触。

公开(公告)号：US06329281B1

公开(公告)日：2001-12-11

申请号：US09454909

申请日：1999-12-03

申请人： Steven Alan Lytle ,  Mary Drummond Roby ,  Daniel Joseph Vitkavage

发明人： Steven Alan Lytle ,  Mary Drummond Roby ,  Daniel Joseph Vitkavage

IPC分类号： H01L214763

CPC分类号： H01L21/76807 ,  H01L21/76813

摘要： The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.

摘要翻译： 本发明利用选择性覆盖层来提供更有效地制造双镶嵌多层互连结构。 选择性覆盖层用作保护掩模，其防止复合层的上层在形成多层互连期间被侵蚀。 本发明还解决了与全通孔第一和部分通孔第一制造方法相关的一些问题，因为选择性覆盖层能够形成有效的深部分通孔，同时防止在随后的制造步骤中沉积未显影的光致抗蚀剂。 本发明还在沉积导电层之后在双镶嵌结构的平面化和抛光期间提供了优点，因为选择性覆盖层允许有效的平面化而不损失沟槽深度控制。

公开(公告)号：US5712176A

公开(公告)日：1998-01-27

申请号：US497470

申请日：1995-06-30

申请人： Steven Alan Lytle ,  Yaw Samuel Obeng ,  Eric John Persson

发明人： Steven Alan Lytle ,  Yaw Samuel Obeng ,  Eric John Persson

IPC分类号： H01L21/28 ,  H01L21/3215 ,  H01L21/8234

CPC分类号： H01L21/28035 ,  H01L21/32155 ,  H01L21/823437

摘要： A process for forming a P.sub.2 O.sub.5 layer suitable for diffusion doping polysilicon gates is disclosed. The inventive process has a reduced thermal budget and helps to eliminate subsequent gate oxide roughness.

摘要翻译： 公开了一种用于形成适用于扩散掺杂多晶硅栅极的P2O5层的工艺。 本发明的方法具有降低的热预算并且有助于消除随后的栅极氧化物粗糙度。

公开(公告)号：US20120108068A1

公开(公告)日：2012-05-03

申请号：US13288756

申请日：2011-11-03

申请人： Steven Alan Lytle

发明人： Steven Alan Lytle

IPC分类号： H01L21/311

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76816

摘要： A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.

摘要翻译： 通过在光刻图案上形成在低温下沉积的ALD膜的侧壁来均匀收缩孔和空间几何形状的方法。

公开(公告)号：US07160799B2

公开(公告)日：2007-01-09

申请号：US10603041

申请日：2003-06-24

申请人： Steven Alan Lytle ,  Thomas Michael Wolf ,  Allen Yen

发明人： Steven Alan Lytle ,  Thomas Michael Wolf ,  Allen Yen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L23/528 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

摘要翻译： 本发明包括一种用于制造集成电路的方法，包括在导电材料上提供包括电介质层的衬底，在电介质层上沉积硬掩模，在硬掩模上施加第一光致抗蚀剂并对光栅定义沟槽，蚀刻硬掩模并部分地 蚀刻电介质以形成具有底部的沟槽，剥离光致抗蚀剂，施加第二光致抗蚀剂并且在沟槽之间照明定义狭缝，从沟槽的底部选择性地蚀刻电介质到下面的导电材料。 硬掩模和第二光致抗蚀剂均用作掩模。 之后，形成与底层金属的连接，由此形成集成电路。

公开(公告)号：US08728945B2

公开(公告)日：2014-05-20

申请号：US13288756

申请日：2011-11-03

申请人： Steven Alan Lytle

发明人： Steven Alan Lytle

IPC分类号： H01L21/311

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76816

摘要： A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.

摘要翻译： 通过在光刻图案上形成在低温下沉积的ALD膜的侧壁来均匀收缩孔和空间几何形状的方法。