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    Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities
    1.
    发明授权
    Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities 有权
    通过起皱包含高比例杂质的层来形成集成电路电极和电容器的方法

    公开(公告)号：US07700454B2

    公开(公告)日：2010-04-20

    申请号：US11462178

    申请日：2006-08-03

    申请人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

    发明人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

    IPC分类号： H01L21/20

    CPC分类号： H01L28/84 ,  H01L27/1085

    摘要： A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.

    摘要翻译： 提供一种制造均匀起皱的电容器下电极而不需要进行高温热处理的方法，以及制造包括均匀起皱的电容器下电极的电容器的方法。 形成第一导电层。 然后，在第一导电层上形成包含约20％至约50％的杂质的第二导电层。 接下来，通过热处理第二导电层，至少一些杂质从第二导电层排出。 由于来自第二导电层的杂质的耗尽，第二导电层的表面起皱。 然后可以形成电介质层和上电容器电极。

    METHODS OF FORMING INTEGRATED CIRCUIT ELECTRODES AND CAPACITORS BY WRINKLING A LAYER THAT INCLUDES A HIGH PERCENTAGE OF IMPURITIES
    2.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT ELECTRODES AND CAPACITORS BY WRINKLING A LAYER THAT INCLUDES A HIGH PERCENTAGE OF IMPURITIES 有权
    形成集成电路电容器和电容器的方法，包括一个包含高达百分之百的包层

    公开(公告)号：US20060263977A1

    公开(公告)日：2006-11-23

    申请号：US11462178

    申请日：2006-08-03

    申请人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

    发明人： Wan-don Kim ,  Jae-hyun Joo ,  Seok-jun Won ,  Jung-hee Chung ,  Jin-yong Kim ,  Suk-jin Chung

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/84 ,  H01L27/1085

    摘要： A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.

    摘要翻译： 提供一种制造均匀起皱的电容器下电极而不需要执行高温热处理的方法，以及制造包括均匀起皱的电容器下电极的电容器的方法。 形成第一导电层。 然后，在第一导电层上形成包含约20％至约50％的杂质的第二导电层。 接下来，通过热处理第二导电层，至少一些杂质从第二导电层排出。 由于来自第二导电层的杂质的耗尽，第二导电层的表面起皱。 然后可以形成电介质层和上电容器电极。

    Methods for manufacturing integrated circuit metal-insulator-metal capacitors including hemispherical grain lumps
    3.
    发明授权
    Methods for manufacturing integrated circuit metal-insulator-metal capacitors including hemispherical grain lumps 失效
    用于制造集成电路金属 - 绝缘体 - 金属电容器的方法包括半球形颗粒块

    公开(公告)号：US06677217B2

    公开(公告)日：2004-01-13

    申请号：US10180277

    申请日：2002-06-26

    申请人： Jae-hyun Joo ,  Wan-don Kim ,  Seok-jun Won ,  Soon-yeon Park

    发明人： Jae-hyun Joo ,  Wan-don Kim ,  Seok-jun Won ,  Soon-yeon Park

    IPC分类号： H01L2120

    CPC分类号： H01L28/84 ,  H01L28/55 ,  H01L28/60 ,  H01L28/90

    摘要： The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

    摘要翻译： MIM电容器的有效面积通过形成包括半球形颗粒的下部电极而增加。 通过在氧气和/或氮气气氛中热处理金属层，从而氧化金属层的表面或生长金属层的晶粒，形成半球状晶粒块。 MIM电容器可以由Pt，Ru，Rh，Os，Ir或Pd形成，并且半球状晶粒块可以由Pt，Ru，Rh，Os，Ir或Pd形成。 由于金属层在下电极的形成期间主要进行热处理，所以可以降低由于在形成介电层和上层之后的热处理而使下电极的表面形态快速变化的程度 电极。

    Methods for manufacturing storage nodes of stacked capacitors
    4.
    发明授权
    Methods for manufacturing storage nodes of stacked capacitors 有权

    公开(公告)号：US06613629B2

    公开(公告)日：2003-09-02

    申请号：US10213856

    申请日：2002-08-07

    申请人： Wan-don Kim ,  Cha-young Yoo ,  Jae-hyun Joo ,  Seok-jun Won

    发明人： Wan-don Kim ,  Cha-young Yoo ,  Jae-hyun Joo ,  Seok-jun Won

    IPC分类号： H01L218242

    CPC分类号： H01L28/60 ,  H01L27/10852 ,  H01L28/55

    摘要： Methods for manufacturing a node of a stacked capacitor are provided. A first dielectric layer having a contact plug therein is formed on an integrated circuit substrate. A second dielectric layer including a storage node hole adjacent the contact plug is formed on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer on the second dielectric layer is removed to provide a conductive storage node in the storage node hole. After the conductive layer on the second dielectric layer is removed, the conductive storage node is heat treated to reflow the conductive storage node before additional layers are formed on the conductive storage node.

    SEMICONDUCTOR DEVICES HAVING A CONTACT PLUG AND FABRICATION METHODS THEREOF
    7.
    发明申请
    SEMICONDUCTOR DEVICES HAVING A CONTACT PLUG AND FABRICATION METHODS THEREOF 有权
    具有接触插头的半导体器件及其制造方法

    公开(公告)号：US20090072350A1

    公开(公告)日：2009-03-19

    申请号：US12270286

    申请日：2008-11-13

    申请人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

    发明人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

    IPC分类号： H01L29/92 ,  H01L21/20

    CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L28/60

    摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

    摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括形成在支撑层上并具有接触孔的绝缘层。 第一接触塞形成在接触孔的内壁和底部上。 第二接触插塞将接触孔埋入并形成在第一接触插塞上。 导电层连接到第一接触插塞和第二接触插塞。 形成在接触孔底部的第一接触塞的底部厚度比形成在接触孔的内壁上的第一接触塞的内壁厚度大。

    Semiconductor devices having a contact plug and fabrication methods thereof
    8.
    发明授权
    Semiconductor devices having a contact plug and fabrication methods thereof 有权
    具有接触塞的半导体器件及其制造方法

    公开(公告)号：US07781819B2

    公开(公告)日：2010-08-24

    申请号：US12270286

    申请日：2008-11-13

    申请人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

    发明人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

    IPC分类号： H01L29/92

    CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L28/60

    摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

    摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括形成在支撑层上并具有接触孔的绝缘层。 第一接触塞形成在接触孔的内壁和底部上。 第二接触插塞将接触孔埋入并形成在第一接触插塞上。 导电层连接到第一接触插塞和第二接触插塞。 形成在接触孔底部的第一接触塞的底部厚度比形成在接触孔的内壁上的第一接触塞的内壁厚度大。

    Integrated circuit devices having a metal-insulator-metal (MIM) capacitor
    9.
    发明申请
    Integrated circuit devices having a metal-insulator-metal (MIM) capacitor 审中-公开
    具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件

    公开(公告)号：US20050161727A1

    公开(公告)日：2005-07-28

    申请号：US11083874

    申请日：2005-03-18

    申请人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

    发明人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/76 ,  H01L21/20

    CPC分类号： H01L28/60 ,  H01L27/10855 ,  H01L28/91

    摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

    摘要翻译： 在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。 电介质层位于下电极上，电容器的上电极位于电介质层上。 在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。 接触塞设置在阻挡层上的孔中。 电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。 电介质层位于下电极上，电容器的上电极位于电介质层上。

    Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor
    10.
    发明授权
    Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor 有权
    形成具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件的方法

    公开(公告)号：US06884673B2

    公开(公告)日：2005-04-26

    申请号：US10160646

    申请日：2002-05-31

    申请人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

    发明人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/60 ,  H01L27/10855 ,  H01L28/91

    摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

    摘要翻译： 在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。 电介质层位于下电极上，电容器的上电极位于电介质层上。 在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。 接触塞设置在阻挡层上的孔中。 电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。 电介质层位于下电极上，电容器的上电极位于电介质层上。