公开(公告)号：US06740960B1

公开(公告)日：2004-05-25

申请号：US10231752

申请日：2002-08-29

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L23495

CPC分类号： H01L23/49827 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02333 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48465 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.

摘要翻译： 提供了一种芯片级半导体封装和一种制造该封装的方法。 该封装包括半导体管芯和连接到管芯的表面的柔性电路。 柔性电路包括具有密集阵列的外部触点的聚合物基板和与外部触点电连通的导体图案。 封装还包括被配置为在管芯触头（例如，焊盘）之间提供分开的电路径的互连件以及柔性电路上的导体。 提供了互连的几个不同实施例，包括：在裸片上的凸起接触，用导电粘合剂层粘合到柔性电路导体上; 导体上的聚合物凸块或模具接触件以半固化状态施加，然后完全固化; 使用焊接工具彼此接合的管芯触点和导体上的焊料凸块; 使用金属凸块和引线接合或球焊接装置形成的导体和裸片接触之间的铆钉状接合连接; 导体和裸片接点之间的单点接合连接，用接合工具形成; 以及导体和裸片接触之间的引线键合。

公开(公告)号：US06614104B2

公开(公告)日：2003-09-02

申请号：US10264047

申请日：2002-10-04

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L2302

CPC分类号： H01L24/06 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly. A method for fabricating the package includes the steps of providing the conductive layer having the conductive traces, attaching the die to the conductive traces, forming the first insulating layer on the conductive layer, forming the second insulating layer on the die, forming the conductive vias through the insulating layers, and then forming the external contacts on the planar surfaces of the insulating layers.

摘要翻译： 半导体封装包括基板和半导体芯片引线，该半导体芯片引线与基板接合或交替地倒装芯片接合。 衬底包括三个分开的层，包括具有导电迹线图案的导电层，覆盖导电迹线的第一绝缘层和覆盖管芯的第二绝缘层。 绝缘层还包括具有外部触点的平面表面，以及与外部触点和导电迹线电连通的导电通孔。 外部触点具有匹配的图案，使得封装可以堆叠在基本相同的封装上以形成堆叠的电子组件。 此外，堆叠组件中的封装可以具有不同的电路配置，并且可以在组件中执行不同的功能。 制造封装的方法包括以下步骤：提供具有导电迹线的导电层，将裸片附着到导电迹线上，在导电层上形成第一绝缘层，在裸片上形成第二绝缘层，形成导电通孔 通过绝缘层，然后在绝缘层的平坦表面上形成外部接触。

公开(公告)号：US06501165B1

公开(公告)日：2002-12-31

申请号：US10161839

申请日：2002-06-03

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L2312

CPC分类号： H01L24/06 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly. A method for fabricating the package includes the steps of providing the conductive layer having the conductive traces, attaching the die to the conductive traces, forming the first insulating layer on the conductive layer, forming the second insulating layer on the die, forming the conductive vias through the insulating layers, and then forming the external contacts on the planar surfaces of the insulating layers.

摘要翻译： 半导体封装包括基板和半导体芯片引线，该半导体芯片引线与基板接合或交替地倒装芯片接合。 衬底包括三个分开的层，包括具有导电迹线图案的导电层，覆盖导电迹线的第一绝缘层和覆盖管芯的第二绝缘层。 绝缘层还包括具有外部触点的平面表面，以及与外部触点和导电迹线电连通的导电通孔。 外部触点具有匹配的图案，使得封装可以堆叠在基本相同的封装上以形成堆叠的电子组件。 此外，堆叠组件中的封装可以具有不同的电路配置，并且可以在组件中执行不同的功能。 制造封装的方法包括以下步骤：提供具有导电迹线的导电层，将裸片附着到导电迹线上，在导电层上形成第一绝缘层，在裸片上形成第二绝缘层，形成导电通孔 通过绝缘层，然后在绝缘层的平坦表面上形成外部接触。

公开(公告)号：US06368896B2

公开(公告)日：2002-04-09

申请号：US09298514

申请日：1999-04-23

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L2144

CPC分类号： H01L23/49827 ,  H01L23/4985 ,  H01L2224/02333 ,  H01L2224/73215 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15173

摘要： A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.

摘要翻译： 提供了一种芯片级半导体封装和一种制造该封装的方法。 该封装包括半导体管芯和连接到管芯的表面的柔性电路。 柔性电路包括具有密集阵列的外部触点的聚合物基板和与外部触点电连通的导体图案。 封装还包括被配置为在管芯触头（例如，焊盘）之间提供分开的电路径的互连件以及柔性电路上的导体。 提供了互连的几个不同实施例，包括：在裸片上的凸起接触，用导电粘合剂层结合到柔性电路导体上; 导体上的聚合物凸块或模具接触件以半固化状态施加，然后完全固化; 使用焊接工具彼此接合的管芯触点和导体上的焊料凸块; 使用金属凸块和引线接合或球焊接装置形成的导体和裸片接触之间的铆钉状接合连接; 导体和裸片接点之间的单点接合连接，用接合工具形成; 以及导体和裸片接触之间的引线键合。

公开(公告)号：US06210993B1

公开(公告)日：2001-04-03

申请号：US09349417

申请日：1999-07-06

申请人： Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  Mike Brooks ,  Eugene Cloud

发明人： Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  Mike Brooks ,  Eugene Cloud

IPC分类号： H01L2144

CPC分类号： H01L25/0657 ,  H01L23/4985 ,  H01L24/72 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor package and a method of fabrication are provided. The package includes multiple semiconductor dice contained in a housing, and mounted on edge to a substrate. Each die includes a polymer interconnect which attaches to a face of the die, and wraps around an end (or side) of the die. The polymer interconnect includes a flexible polymer tape with patterns of conductors. The conductors include microbumps for bonding to the die bond pads, and edge contacts for electrical connection to mating contacts on the substrate. The package also includes a force applying mechanism for biasing the dice against the substrate. In alternate embodiments, the polymer interconnect includes resilient edge contacts, cantilevered edge contacts, or multi level edge contacts.

摘要翻译： 提供半导体封装和制造方法。 封装包括容纳在外壳中的多个半导体裸片，并且安装在边缘到基板上。 每个管芯包括连接到管芯的表面并且围绕管芯的端部（或侧面）的聚合物互连。 聚合物互连包括具有导体图案的柔性聚合物带。 导体包括用于与芯片接合焊盘接合的微胶片，以及用于与衬底上的配合触点电连接的边缘触点。 该包装还包括用于将骰子偏压抵靠衬底的施力机构。 在替代实施例中，聚合物互连包括弹性边缘触点，悬臂边缘触点或多级边缘触点。

公开(公告)号：US06975037B2

公开(公告)日：2005-12-13

申请号：US10871925

申请日：2004-06-18

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L23/498 ,  H01L29/40

CPC分类号： H01L23/49827 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02333 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48465 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.

摘要翻译： 提供了一种芯片级半导体封装和一种制造该封装的方法。 该封装包括半导体管芯和连接到管芯的表面的挠性电路。 柔性电路包括具有密集阵列的外部触点的聚合物基板和与外部触点电连通的导体图案。 封装还包括被配置为在管芯触头（例如，焊盘）之间提供分开的电路径的互连件以及柔性电路上的导体。 提供了互连的几个不同实施例，包括：在裸片上的凸起接触，用导电粘合剂层结合到柔性电路导体上; 导体上的聚合物凸块或模具接触件以半固化状态施加，然后完全固化; 使用焊接工具彼此接合的管芯触点和导体上的焊料凸块; 使用金属凸块和引线接合或球焊接装置形成的导体和裸片接触之间的铆钉状接合连接; 导体和裸片接点之间的单点接合连接，用接合工具形成; 以及导体和裸片接触之间的引线键合。

公开(公告)号：US06911355B2

公开(公告)日：2005-06-28

申请号：US10754285

申请日：2004-01-09

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L23/498 ,  H01L21/44

CPC分类号： H01L23/49827 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02333 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48465 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.

公开(公告)号：US06465877B1

公开(公告)日：2002-10-15

申请号：US09536827

申请日：2000-03-27

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L23495

CPC分类号： H01L23/49827 ,  H01L23/4985 ,  H01L2224/02333 ,  H01L2224/73215 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15173

摘要： A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.

摘要翻译： 提供了一种芯片级半导体封装和一种制造该封装的方法。 该封装包括半导体管芯和连接到管芯的表面的柔性电路。 柔性电路包括具有密集阵列的外部触点的聚合物基板和与外部触点电连通的导体图案。 封装还包括被配置为在管芯触头（例如，焊盘）之间提供分开的电路径的互连件以及柔性电路上的导体。 提供了互连的几个不同实施例，包括：在裸片上的凸起接触，用导电粘合剂层结合到柔性电路导体上; 导体上的聚合物凸块或模具接触件以半固化状态施加，然后完全固化; 使用焊接工具彼此接合的管芯触点和导体上的焊料凸块; 使用金属凸块和引线接合或球焊接装置形成的导体和裸片接触之间的铆钉状接合连接; 导体和裸片接点之间的单点接合连接，用接合工具形成; 以及导体和裸片接触之间的引线键合。

公开(公告)号：US06451624B1

公开(公告)日：2002-09-17

申请号：US09923144

申请日：2001-08-07

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L2144

CPC分类号： H01L24/06 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly. A method for fabricating the package includes the steps of providing the conductive layer having the conductive traces, attaching the die to the conductive traces, forming the first insulating layer on the conductive layer, forming the second insulating layer on the die, forming the conductive vias through the insulating layers, and then forming the external contacts on the planar surfaces of the insulating layers.

公开(公告)号：US06271056B1

公开(公告)日：2001-08-07

申请号：US09259861

申请日：1999-03-01

申请人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

发明人： Warren M. Farnworth ,  Alan G. Wood ,  Mike Brooks

IPC分类号： H01L2144

CPC分类号： H01L24/06 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor package and a method for fabricating the package are provided. The package includes multiple substrates in a stacked configuration, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing sides of the substrate, and interconnected by interlevel conductors through the substrate. In the package, the external contacts on a first substrate are bonded to the contact pads on an adjacent second substrate, so that all of the dice in the package are interconnected. The fabrication process includes forming multiple substrates on a panel, mounting the dice to the substrates, stacking and bonding the panels to one another, and then separating the substrates from the stacked panels to form the packages.

摘要翻译： 提供半导体封装和制造封装的方法。 该封装包括堆叠构造的多个衬底，每个衬底上安装有半导体管芯。 每个衬底包括形成在衬底的相对侧上的外部触点和接触焊盘的匹配图案，并且通过穿过衬底的层间导体互连。 在封装中，第一衬底上的外部接触件接合到相邻第二衬底上的接触焊盘，使得封装中的所有裸片相互连接。 制造工艺包括在面板上形成多个基板，将芯片安装到基板上，将面板彼此堆叠和粘合，然后将基板与堆叠的面板分开以形成封装。