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    Manufacturing method for an integrated semiconductor structure
    2.
    发明申请
    Manufacturing method for an integrated semiconductor structure 失效
    集成半导体结构的制造方法

    公开(公告)号：US20070281417A1

    公开(公告)日：2007-12-06

    申请号：US11443652

    申请日：2006-05-31

    申请人： Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Daniel Koehler ,  Joern Regul

    发明人： Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Daniel Koehler ,  Joern Regul

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

    摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said said memory cell region; removing said said mask layer and said first protective layer from said memory cell region; forming a first contact hole between two neighboring gate stacks in said memory cell region, said first contact hole exposing a contact area; forming at least one other contact hole in said peripheral device region, said at least one other contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one other contact hole with a respective contact plug.

    摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：在存储单元区域中提供具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域和外围设备区域上沉积由碳制成的或由含碳材料制成的第一保护层; 在所述存储单元区域中的所述第一保护层上形成掩模层; 通过在蚀刻步骤中去除所述外围设备区域中的所述第一保护层，在所述外围设备区域中暴露所述至少一个栅极堆叠的所述盖，其中所述掩模层用作所述存储单元区域中的掩模; 从所述存储单元区域中去除所述掩模层和所述第一保护层; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔，所述第一接触孔暴露接触区域; 在所述外围设备区域中形成至少另一个接触孔，所述至少一个其它接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或位于所述栅极堆叠中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少一个其它接触孔。

    Solenoid valve
    5.
    发明授权
    Solenoid valve 失效
    电磁阀

    公开(公告)号：US06827332B2

    公开(公告)日：2004-12-07

    申请号：US10279046

    申请日：2002-10-22

    申请人： Juergen Hanneke ,  Daniel Koehler

    发明人： Juergen Hanneke ,  Daniel Koehler

    IPC分类号： F16K3102

    CPC分类号： F02M61/168 ,  F02M47/027 ,  F02M63/0017 ,  F02M2200/8053

    摘要： A solenoid valve having a magnet assembly and an injector body connected thereto, the magnet assembly and the injector body being joined together using a crimped retaining ring as the connecting element.

    摘要翻译： 一种具有磁体组件和连接到其上的喷射器主体的电磁阀，磁体组件和喷射器主体使用卷曲保持环作为连接元件而连接在一起。

    Method for Fabricating a Structure for a Semiconductor Component, and Semiconductor Component
    7.
    发明申请
    Method for Fabricating a Structure for a Semiconductor Component, and Semiconductor Component 审中-公开
    制造半导体元件结构的方法和半导体元件

    公开(公告)号：US20080085606A1

    公开(公告)日：2008-04-10

    申请号：US11867724

    申请日：2007-10-05

    申请人： Dominik Fischer ,  Werner Jacobs ,  Daniel Koehler ,  Alfred Kersch ,  Winfried Sabisch

    发明人： Dominik Fischer ,  Werner Jacobs ,  Daniel Koehler ,  Alfred Kersch ,  Winfried Sabisch

    IPC分类号： H01L21/461

    CPC分类号： H01L21/76816 ,  H01L21/31144

    摘要： In one aspect, the invention provides a fabrication method. Before the fabrication of the structure, a mask layer, for example a hard mask, is applied to a layer. The mask layer has at least two layers composed of materials that can be etched selectively with respect to one another. In a first etching process, the structure is introduced into the layer. Subsequently, the first etching process is interrupted at a point in time in order to etch away a topmost layer of the hard mask selectively with respect to the underlying layer by means of a second etching process and, subsequently, the first etching process is continued for fabricating the structure with the new topmost layer.

    摘要翻译： 一方面，本发明提供一种制造方法。 在制造结构之前，将掩模层（例如硬掩模）施加到层上。 掩模层具有由能够相对于彼此选择性地蚀刻的材料组成的至少两层。 在第一蚀刻工艺中，将结构引入层中。 随后，第一蚀刻工艺在某个时间点被中断，以便通过第二蚀刻工艺相对于下面的层选择性蚀刻掉硬掩模的最上层，并且随后继续进行第一蚀刻工艺 用新的最上层制造结构。

    Memory Device and Method of Manufacturing the Same
    9.
    发明申请
    Memory Device and Method of Manufacturing the Same 审中-公开
    存储器件及其制造方法

    公开(公告)号：US20070161277A1

    公开(公告)日：2007-07-12

    申请号：US11678735

    申请日：2007-02-26

    申请人： Peter Baars ,  Klaus Muemmler ,  Daniel Koehler

    发明人： Peter Baars ,  Klaus Muemmler ,  Daniel Koehler

    IPC分类号： H01R29/00

    CPC分类号： H01L28/91 ,  H01L21/76816 ,  H01L27/10817 ,  H01L27/10894

    摘要： A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from the channel and adapted to control the conductivity of the channel. The access transistor is at least partially formed in the semiconductor substrate. The storage capacitor is adapted to be accessed by the access transistor. The storage capacitor includes at least first and second storage electrodes and at least a capacitor dielectric disposed between the first and the second storage electrodes. Each of the first and the second storage electrodes is disposed above the substrate surface.

    摘要翻译： 存储器件包括存储单元阵列和用于存储信息的存储电容器。 每个存储单元包括存取晶体管。 存取晶体管包括第一和第二源极/漏极区域，设置在第一和第二源极/漏极区域之间的沟道以及与沟道电绝缘并适于控制沟道的导电性的栅电极。 存取晶体管至少部分地形成在半导体衬底中。 存储电容适于由存取晶体管访问。 存储电容器至少包括第一和第二存储电极以及设置在第一和第二存储电极之间的至少一个电容器电介质。 第一和第二存储电极中的每一个设置在基板表面上方。