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    Formation of a disposable spacer to post dope a gate conductor
    2.
    发明授权
    Formation of a disposable spacer to post dope a gate conductor 失效
    一次性间隔件的形成以喷涂一个栅极导体

    公开(公告)号：US07229885B2

    公开(公告)日：2007-06-12

    申请号：US10752386

    申请日：2004-01-06

    申请人： David V. Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    发明人： David V. Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/28035 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed round the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion regions.

    摘要翻译： 提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。 该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。 后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。 在第一栅极层和第二一次性层周围形成脂肪间隔物。 去除第二一次性层，并且将离子注入第一栅极层中以在栅极电介质层上方的栅极中提供额外的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

    Device component forming method with a trim step prior to sidewall image transfer (SIT) processing
    6.
    发明申请
    Device component forming method with a trim step prior to sidewall image transfer (SIT) processing 审中-公开
    在侧壁图像转印（SIT）处理之前具有修整步骤的装置部件形成方法

    公开(公告)号：US20120208356A1

    公开(公告)日：2012-08-16

    申请号：US13456282

    申请日：2012-04-26

    申请人： Toshiharu Furukawa ,  David V. Horak ,  Charles W. Koburger, III ,  Qiqing C. Ouyang

    发明人： Toshiharu Furukawa ,  David V. Horak ,  Charles W. Koburger, III ,  Qiqing C. Ouyang

    IPC分类号： H01L21/20 ,  H01L21/302

    CPC分类号： H01L21/28132 ,  H01L21/0337 ,  H01L21/0338 ,  H01L29/66795

    摘要： Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.

    摘要翻译： 公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。 通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，需要修剪蒙版对准 亚光刻特征以形成具有离散片段的硬掩模图案。 在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。 在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。 然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

    Phase change memory cell with vertical transistor
    9.
    发明授权
    Phase change memory cell with vertical transistor 有权
    具有垂直晶体管的相变存储单元

    公开(公告)号：US07932167B2

    公开(公告)日：2011-04-26

    申请号：US11771457

    申请日：2007-06-29

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    IPC分类号： H01L21/44

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

    摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

    摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

    VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC
    10.
    发明申请
    VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC 审中-公开
    垂直型材FinFET通过薄型电介质形成的FinFET栅极

    公开(公告)号：US20090321833A1

    公开(公告)日：2009-12-31

    申请号：US12145616

    申请日：2008-06-25

    申请人： Veeraraghaven S. Basker ,  Hariklia Deligianni ,  Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Veeraraghaven S. Basker ,  Hariklia Deligianni ,  Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.

    摘要翻译： 公开了通过在薄栅极电介质上电镀制造垂直轮廓FinFET栅电极的方法。 在一个实施例中，一种用于形成晶体管的方法包括：提供包括半导体衬底和在衬底上方延伸的半导体鳍片结构的半导体形貌; 在半导体拓扑的暴露表面上形成栅极电介质; 在半导体形貌上图案化掩模，使得仅限定限定要形成栅电极的位置的栅极电介质的选择部分; 以及在所述栅极电介质的所述选择部分上镀覆金属材料以在所述鳍结构的一部分上形成栅电极。