公开(公告)号：US20100164102A1

公开(公告)日：2010-07-01

申请号：US12317887

申请日：2008-12-30

申请人： Willy Rachmady ,  Been-Yin Jin ,  Ravi Pillarisetty ,  Robert Chau

发明人： Willy Rachmady ,  Been-Yin Jin ,  Ravi Pillarisetty ,  Robert Chau

IPC分类号： H01L29/06 ,  H01L21/34

CPC分类号： H01L21/02532 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/31658 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention describes a method of and an apparatus for providing a wafer, the wafer including Silicon; etching trenches in the wafer to form Silicon fins; filling Silicon Oxide in the trenches; planarizing the Silicon Oxide; recessing the Silicon Oxide to a first thickness to form exposed Silicon pedestals from the Silicon fins; depositing SiGe over the exposed Silicon pedestal; recessing the Silicon Oxide to a second thickness; undercutting the exposed Silicon pedestals to form necked-in Silicon pedestals; oxidizing thermally and annealing the SiGe; and forming Germanium nanowires.

摘要翻译： 本发明描述了一种用于提供晶片的方法和装置，晶片包括硅; 蚀刻晶片中的沟槽以形成硅片; 在沟槽中填充氧化硅; 平面化氧化硅; 将氧化硅凹入第一厚度以从硅片形成暴露的硅基座; 在暴露的硅基座上沉积SiGe; 将氧化硅凹入第二厚度; 将暴露的硅基底切割成颈缩的硅基座; 对SiGe进行热氧化和退火; 并形成锗纳米线。

公开(公告)号：US20140061589A1

公开(公告)日：2014-03-06

申请号：US14057204

申请日：2013-10-18

申请人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/775

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US08592803B2

公开(公告)日：2013-11-26

申请号：US13442098

申请日：2012-04-09

申请人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/06 ,  H01L29/778

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

公开(公告)号：US20120193609A1

公开(公告)日：2012-08-02

申请号：US13442098

申请日：2012-04-09

申请人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/66

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US20130334499A1

公开(公告)日：2013-12-19

申请号：US13957965

申请日：2013-08-02

申请人： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yin Jin ,  Marko Radosavljevic ,  Willy Rachmady

发明人： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yin Jin ,  Marko Radosavljevic ,  Willy Rachmady

IPC分类号： H01L29/06 ,  H01L29/775 ,  H01L21/762

CPC分类号： H01L29/06 ,  B82Y99/00 ,  H01L21/76205 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7854

摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

摘要翻译： 提供了一种方法。 该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。

公开(公告)号：US20130270512A1

公开(公告)日：2013-10-17

申请号：US13976411

申请日：2011-12-19

申请人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

发明人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US09123567B2

公开(公告)日：2015-09-01

申请号：US13976411

申请日：2011-12-19

申请人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

发明人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/78

CPC分类号： H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

摘要翻译： 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够为给定的布局区域提供显着的驱动电流。

公开(公告)号：US20140175378A1

公开(公告)日：2014-06-26

申请号：US13722746

申请日：2012-12-20

申请人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van Le ,  Matthew Metz ,  Jack Kavalieros ,  RAVI PILLARISETTY ,  Sanaz Gardner ,  SANSAPTAK DASGUPTA ,  Willy Rachmady ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  Gilbert Dewey ,  Marc French ,  JESSICA KACHIAN ,  SATYARTH SURI ,  Robert Chau

发明人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van Le ,  Matthew Metz ,  Jack Kavalieros ,  RAVI PILLARISETTY ,  Sanaz Gardner ,  SANSAPTAK DASGUPTA ,  Willy Rachmady ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  Gilbert Dewey ,  Marc French ,  JESSICA KACHIAN ,  SATYARTH SURI ,  Robert Chau

IPC分类号： H01L21/20 ,  H01L21/764

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/76232

摘要： An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.

摘要翻译： 实施例包括将材料沉积到衬底上，其中材料包括与衬底（例如Si衬底上的III-V或IV外延（EPI）材料）不同的晶格常数。 一个实施例包括形成在沟槽内的EPI层，其具有随着沟槽向上延伸而变窄的壁。 实施例包括使用多个生长温度在沟槽内形成的EPI层。 当温度变化时，在EPI层中形成的缺陷屏障在沟槽内和缺陷屏障之下包含缺陷。 缺陷屏障之上和沟槽内的EPI层相对无缺陷。 一个实施方案包括在沟槽内退火以引发缺陷湮灭的EPI层。 一个实施例包括形成在沟槽内并覆盖有相对无缺陷的EPI层（仍包含在沟槽中）的EPI超晶格。 本文描述了其它实施例。

公开(公告)号：US08575653B2

公开(公告)日：2013-11-05

申请号：US12924307

申请日：2010-09-24

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

IPC分类号： H01L29/66

CPC分类号： H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/151 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US20120074386A1

公开(公告)日：2012-03-29

申请号：US12924307

申请日：2010-09-24

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

IPC分类号： H01L29/775 ,  H01L21/336

CPC分类号： H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/151 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

摘要翻译： 公开了用于形成非平面量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现并且包括翅片结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs）和量子阱层。 在量子阱结构中形成翅片结构，并且在翅片结构上设置界面层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。