公开(公告)号：US20120074386A1

公开(公告)日：2012-03-29

申请号：US12924307

申请日：2010-09-24

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

IPC分类号： H01L29/775 ,  H01L21/336

CPC分类号： H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/151 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

摘要翻译： 公开了用于形成非平面量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现并且包括翅片结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs）和量子阱层。 在量子阱结构中形成翅片结构，并且在翅片结构上设置界面层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US08575653B2

公开(公告)日：2013-11-05

申请号：US12924307

申请日：2010-09-24

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert Chau

IPC分类号： H01L29/66

CPC分类号： H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/151 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US09136343B2

公开(公告)日：2015-09-15

申请号：US13749139

申请日：2013-01-24

申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78609 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

摘要翻译： 描述具有锗或III-V族有源层的深栅极全面半导体器件。 例如，非平面半导体器件包括设置在衬底上的异质结构。 异质结构包括不同组成的上层和下层之间的异质结。 有源层设置在杂结构上方，并且具有与异质结构的上层和下层不同的组成。 栅电极堆叠设置在有源层的沟道区上并完全包围有源层的沟道区，并且设置在上层中的沟槽中，并且至少部分地设置在异质结构的下层中。 源极和漏极区域设置在栅电极堆叠的任一侧上的有源层和上层中，而不是在下层中。

公开(公告)号：US08987794B2

公开(公告)日：2015-03-24

申请号：US13997118

申请日：2011-12-23

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Jessica S. Kachian

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Jessica S. Kachian

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H01L2029/7858

摘要： A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

摘要翻译： 描述了非平面栅极全面器件及其制造方法。 在一个实施例中，该器件包括具有第一晶格常数的顶表面的衬底。 嵌入的epi源极和漏极区域形成在衬底的顶表面上。 嵌入的epi源极和漏极区具有不同于第一晶格常数的第二晶格常数。 具有第三晶格的沟道纳米线形成在嵌入的epi源极和漏极区之间并耦合到嵌入的epi源极和漏极区。 在一个实施例中，第二晶格常数和第三晶格常数不同于第一晶格常数。 通道纳米线包括最底部的沟道纳米线，并且在最底部的沟道纳米线下方的衬底的顶表面上形成底栅隔离。 在每个通道纳米线上形成栅极电介质层。 在栅极电介质层上形成栅电极并围绕每个沟道纳米线。

公开(公告)号：US20140225065A1

公开(公告)日：2014-08-14

申请号：US13997118

申请日：2011-12-23

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Jessica S. Kachian

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Jessica S. Kachian

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H01L2029/7858

摘要： A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

摘要翻译： 描述了非平面栅极全面器件及其制造方法。 在一个实施例中，该器件包括具有第一晶格常数的顶表面的衬底。 嵌入的epi源极和漏极区域形成在衬底的顶表面上。 嵌入的epi源极和漏极区具有不同于第一晶格常数的第二晶格常数。 具有第三晶格的沟道纳米线形成在嵌入的epi源极和漏极区之间并耦合到嵌入的epi源极和漏极区。 在一个实施例中，第二晶格常数和第三晶格常数不同于第一晶格常数。 通道纳米线包括最底部的沟道纳米线，并且在最底部的沟道纳米线下方的衬底的顶表面上形成底栅隔离。 在每个通道纳米线上形成栅极电介质层。 在栅极电介质层上形成栅电极并围绕每个沟道纳米线。

公开(公告)号：US20140203327A1

公开(公告)日：2014-07-24

申请号：US13749139

申请日：2013-01-24

申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78609 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

摘要翻译： 描述具有锗或III-V族有源层的深栅极全面半导体器件。 例如，非平面半导体器件包括设置在衬底上的异质结构。 异质结构包括不同组成的上层和下层之间的异质结。 有源层设置在杂结构上方，并且具有与异质结构的上层和下层不同的组成。 栅电极堆叠设置在有源层的沟道区上并完全包围有源层的沟道区，并且设置在上层中的沟槽中，并且至少部分地设置在异质结构的下层中。 源极和漏极区域设置在栅电极堆叠的任一侧上的有源层和上层中，而不是在下层中。

公开(公告)号：US08716751B2

公开(公告)日：2014-05-06

申请号：US13631417

申请日：2012-09-28

申请人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

发明人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC分类号： H01L21/02

CPC分类号： H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

摘要翻译： 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US20120161105A1

公开(公告)日：2012-06-28

申请号：US12976126

申请日：2010-12-22

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le

IPC分类号： H01L29/161 ,  H01L21/336 ,  B82Y99/00

CPC分类号： H01L29/66431 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/122 ,  H01L29/7782 ,  H01L29/7848 ,  H01L29/802

摘要： A planar or non-planar quantum well device and a method of forming the quantum well device. The device includes: a buffer region comprising a large band gap material; a uniaxially strained quantum well channel region on the buffer region; an upper barrier region comprising a large band gap material on the quantum well channel region; a gate dielectric on the quantum well channel region; a gate electrode on the gate dielectric; and recessed source and drain regions at respective sides of the gate electrode, the source and drain regions including a junction material having a lattice constant different from a lattice constant of a material of the buffer region. Preferably, the buffer region comprises a Si1-xGex material, and the junction material comprises one of a Si1-yGey material where y is larger than x, or pure germanium, or tin germanium.

摘要翻译： 平面或非平面量子阱器件和形成量子阱器件的方法。 该装置包括：包括大带隙材料的缓冲区; 缓冲区上的单轴应变量子阱沟道区; 在所述量子阱沟道区上包括大带隙材料的上阻挡区; 量子阱沟道区上的栅极电介质; 栅电极上的栅电极; 以及在栅电极的相应侧处的凹陷的源极和漏极区域，源极和漏极区域包括具有与缓冲区域的材料的晶格常数不同的晶格常数的结合材料。 优选地，缓冲区包括Si1-xGex材料，并且所述连接材料包括y大于x的Si 1-y Ga y材料，或纯锗或锡锗中的一种。

公开(公告)号：US09337291B2

公开(公告)日：2016-05-10

申请号：US14821561

申请日：2015-08-07

申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/205 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78609 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

公开(公告)号：US09236476B2

公开(公告)日：2016-01-12

申请号：US13997972

申请日：2011-12-28

申请人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  G11C11/412 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L29/785 ,  G11C11/412 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

摘要： Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了用于堆叠存储器件的晶体管的技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的多个翅片结构，其中，多个翅片结构的单个翅片结构包括设置在半导体衬底上的第一隔离层， 第一隔离层，设置在第一沟道层上的第二隔离层和设置在第二隔离层上的第二沟道层，以及与第一沟道层电容耦合以控制通过第一沟道层的电流的栅极端子 用于第一晶体管，并与第二沟道层电容耦合，以控制通过第二沟道层的电流流向第二晶体管。 可以描述和/或要求保护其他实施例。