NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF
    2.
    发明申请
    NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF 有权
    非平面门全部装置及其制造方法

    公开(公告)号:US20140225065A1

    公开(公告)日:2014-08-14

    申请号:US13997118

    申请日:2011-12-23

    IPC分类号: H01L29/06 H01L29/78 H01L29/66

    摘要: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

    摘要翻译: 描述了非平面栅极全面器件及其制造方法。 在一个实施例中,该器件包括具有第一晶格常数的顶表面的衬底。 嵌入的epi源极和漏极区域形成在衬底的顶表面上。 嵌入的epi源极和漏极区具有不同于第一晶格常数的第二晶格常数。 具有第三晶格的沟道纳米线形成在嵌入的epi源极和漏极区之间并耦合到嵌入的epi源极和漏极区。 在一个实施例中,第二晶格常数和第三晶格常数不同于第一晶格常数。 通道纳米线包括最底部的沟道纳米线,并且在最底部的沟道纳米线下方的衬底的顶表面上形成底栅隔离。 在每个通道纳米线上形成栅极电介质层。 在栅极电介质层上形成栅电极并围绕每个沟道纳米线。