公开(公告)号：US09608055B2

公开(公告)日：2017-03-28

申请号：US13996502

申请日：2011-12-23

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/786 ,  H01L21/28 ,  H01L29/165 ,  H01L29/78 ,  B82Y10/00

CPC分类号： H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

摘要： Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

公开(公告)号：US09159823B2

公开(公告)日：2015-10-13

申请号：US13977188

申请日：2011-12-09

申请人： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

发明人： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

摘要： Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

摘要翻译： 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，所述晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。

公开(公告)号：US20140209865A1

公开(公告)日：2014-07-31

申请号：US13997897

申请日：2011-12-28

申请人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

发明人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

IPC分类号： H01L29/775 ,  H01L29/66

CPC分类号： H01L29/41791 ,  B82Y40/00 ,  B82Y99/00 ,  G11C7/02 ,  H01L23/485 ,  H01L23/535 ,  H01L27/115 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/89 ,  H01L2924/00

摘要： Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

摘要翻译： 本公开的实施例提供了用于减小纳米线晶体管中的寄生电阻的接触技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的隔离层，包括在隔离层上形成的纳米线材料以提供晶体管沟道的沟道层，以及与沟道层耦合的接触点 被配置为在至少一个平面尺寸中围绕所述沟道层的纳米线材料并且为所述晶体管提供源极端子或漏极端子。

公开(公告)号：US08748940B1

公开(公告)日：2014-06-10

申请号：US13717282

申请日：2012-12-17

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L21/20 ,  H01L21/36 ,  H01L29/66 ,  H01L29/06 ,  C23F1/30

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

摘要： Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

摘要翻译： 在那里制造的半导体器件堆叠和器件具有富锗器件层。 富锗器件层设置在衬底之上，其中设置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。 随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。

公开(公告)号：US08710490B2

公开(公告)日：2014-04-29

申请号：US13629178

申请日：2012-09-27

申请人： Ravi Pillarisetty ,  Niti Goel ,  Han Wui Then ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung

发明人： Ravi Pillarisetty ,  Niti Goel ,  Han Wui Then ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung

IPC分类号： H01L29/06 ,  H01L21/02

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/785 ,  H01L29/78696

摘要： Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.

摘要翻译： 描述具有底层寄生泄漏阻挡层的具有锗活性层的半导体器件。 例如，半导体器件包括设置在衬底上方的第一缓冲层。 寄生泄漏屏障设置在第一缓冲层之上。 第二缓冲层设置在寄生泄漏屏障的上方。 锗活性层设置在第二缓冲层上方。 栅电极堆叠设置在锗活性层上方。 源极和漏极区域设置在栅极电极堆叠的任一侧上的寄生泄漏屏障之上。

公开(公告)号：US20140110669A1

公开(公告)日：2014-04-24

申请号：US14060557

申请日：2013-10-22

申请人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert S. Chau

发明人： Willy Rachmady ,  Ravi Pillarisetty ,  Van H. Le ,  Robert S. Chau

IPC分类号： H01L29/775 ,  H01L29/66

CPC分类号： H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/151 ,  H01L29/165 ,  H01L29/267 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

摘要翻译： 公开了用于形成非平面量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现并且包括翅片结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs）和量子阱层。 在量子阱结构中形成翅片结构，并且在翅片结构上设置界面层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US20140091361A1

公开(公告)日：2014-04-03

申请号：US13631417

申请日：2012-09-28

申请人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

发明人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

公开(公告)号：US09590089B2

公开(公告)日：2017-03-07

申请号：US13997162

申请日：2011-12-30

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  Y10S977/762 ,  Y10S977/89 ,  Y10S977/938

摘要： Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

摘要翻译： 本文描述了具有一个或多个活性纳米线和一个或多个非活性纳米线的基于纳米线的栅极全周极晶体管器件。 还描述了制造这种装置的方法。 本发明的一个或多个实施例涉及用于改变包括具有不同数量的纳米线的纳米线堆叠的晶体管结构的栅极宽度的方法。 这些方法包括使一定数量的纳米线无效（即使得电流不流过纳米线），通过切断沟道区，掩埋源区和漏区，或两者。 总之，具有多个纳米线的纳米线基结构的栅极宽度可以通过使一定数量的纳米线无效而保持其它纳米线作为活性而变化。

公开(公告)号：US09159787B2

公开(公告)日：2015-10-13

申请号：US14301281

申请日：2014-06-10

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/786

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

摘要： Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

摘要翻译： 在那里制造的半导体器件堆叠和器件具有富锗器件层。 富锗器件层设置在衬底之上，其中设置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。 随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。

公开(公告)号：US20130341704A1

公开(公告)日：2013-12-26

申请号：US13997162

申请日：2011-12-30

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  Y10S977/762 ,  Y10S977/89 ,  Y10S977/938

摘要： Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

摘要翻译： 本文描述了具有一个或多个活性纳米线和一个或多个非活性纳米线的基于纳米线的栅极全周极晶体管器件。 还描述了制造这种装置的方法。 本发明的一个或多个实施例涉及用于改变包括具有不同数量的纳米线的纳米线堆叠的晶体管结构的栅极宽度的方法。 这些方法包括使一定数量的纳米线无效（即使得电流不流过纳米线），通过切断沟道区，掩埋源区和漏区，或两者。 总之，具有多个纳米线的纳米线基结构的栅极宽度可以通过使一定数量的纳米线无效而保持其它纳米线作为活性而变化。