公开(公告)号：US08603917B2

公开(公告)日：2013-12-10

申请号：US13284546

申请日：2011-10-28

申请人： Woon Seong Kwon ,  Nagarajan Ranganathan

发明人： Woon Seong Kwon ,  Nagarajan Ranganathan

IPC分类号： H01L21/306 ,  B44C1/22

CPC分类号： H01L21/76898 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/321 ,  H01L23/481 ,  H01L2224/16145

摘要： According to embodiments of the present invention, a method of processing a wafer is provided. The wafer includes a plurality of through-wafer interconnects extending from a frontside surface of the wafer to a backside surface of the wafer. The method includes removing a part of wafer material of the back-side such that a portion of the wafer material between the through-wafer interconnects is removed, thereby exposing a portion of the through-wafer interconnects, forming a layer of low-k dielectric material between the through-wafer interconnects, and planarizing the layer of low-k dielectric material such that a surface of the portion of the through-wafer interconnect is exposed.

摘要翻译： 根据本发明的实施例，提供了一种处理晶片的方法。 晶片包括从晶片的前表面延伸到晶片的后侧表面的多个贯穿晶片互连。 该方法包括去除后侧的晶片材料的一部分，使得在晶片间互连之间的晶片材料的一部分被去除，从而暴露一部分透晶片互连，形成低k电介质层 在晶片间互连之间的材料，以及平坦化低k电介质材料层，使得透晶片互连部分的表面露出。

公开(公告)号：US20120178258A1

公开(公告)日：2012-07-12

申请号：US13284546

申请日：2011-10-28

申请人： Woon Seong Kwon ,  Nagarajan Ranganathan

发明人： Woon Seong Kwon ,  Nagarajan Ranganathan

IPC分类号： H01L21/306

CPC分类号： H01L21/76898 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/321 ,  H01L23/481 ,  H01L2224/16145

摘要： According to embodiments of the present invention, a method of processing a wafer is provided. The wafer includes a plurality of through-wafer interconnects extending from a frontside surface of the wafer to a backside surface of the wafer. The method includes removing a part of wafer material of the back-side such that a portion of the wafer material between the through-wafer interconnects is removed, thereby exposing a portion of the through-wafer interconnects, forming a layer of low-k dielectric material between the through-wafer interconnects, and planarizing the layer of low-k dielectric material such that a surface of the portion of the through-wafer interconnect is exposed.

摘要翻译： 根据本发明的实施例，提供了一种处理晶片的方法。 晶片包括从晶片的前表面延伸到晶片的后侧表面的多个贯穿晶片互连。 该方法包括去除后侧的晶片材料的一部分，使得在晶片间互连之间的晶片材料的一部分被去除，从而暴露一部分透晶片互连，形成低k电介质层 在晶片间互连之间的材料，以及平坦化低k电介质材料层，使得透晶片互连部分的表面露出。

公开(公告)号：US20130020713A1

公开(公告)日：2013-01-24

申请号：US13497611

申请日：2009-09-25

申请人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

发明人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/6836 ,  B81B2207/092 ,  B81B2207/093 ,  B81B2207/097 ,  B81C2203/019 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16315 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.

摘要翻译： 在一个实施例中，可以提供晶片级封装。 晶片级封装可以包括包括MEMS器件的器件晶片，设置在器件晶片上的帽晶片，设置在器件晶片和帽晶片之间的至少一个第一互连，并且被配置为在器件晶片和晶片级封装之间提供电连接 帽状晶片和保形密封环，其设置在器件晶片和盖晶片之间并且被配置为围绕至少一个第一互连和MEMS器件，以便为至少一个第一互连和MEMS器件提供保形密封的环境 ，其中所述保形密封环可以被配置为当所述器件晶片可以结合到所述盖晶片时，使其符合所述器件晶片和所述盖晶片的相应合适的表面。 还可以提供一种形成晶片级封装的方法。

公开(公告)号：US08729695B2

公开(公告)日：2014-05-20

申请号：US13497611

申请日：2009-09-25

申请人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

发明人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H01L21/6836 ,  B81B2207/092 ,  B81B2207/093 ,  B81B2207/097 ,  B81C2203/019 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16315 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.

摘要翻译： 在一个实施例中，可以提供晶片级封装。 晶片级封装可以包括包括MEMS器件的器件晶片，设置在器件晶片上的帽晶片，设置在器件晶片和帽晶片之间的至少一个第一互连，并且被配置为在器件晶片和晶片级封装之间提供电连接 帽状晶片和保形密封环，其设置在器件晶片和盖晶片之间并且被配置为围绕至少一个第一互连和MEMS器件，以便为至少一个第一互连和MEMS器件提供保形密封的环境 ，其中所述保形密封环可以被配置为当所述器件晶片可以结合到所述盖晶片时，使其符合所述器件晶片和所述盖晶片的相应合适的表面。 还可以提供一种形成晶片级封装的方法。

公开(公告)号：US20100015008A1

公开(公告)日：2010-01-21

申请号：US12294205

申请日：2007-03-23

申请人： Wee Liat Ong ,  Levent Yobas ,  Kim Cheong Tang ,  Ajay Agarwal ,  Nagarajan Ranganathan

发明人： Wee Liat Ong ,  Levent Yobas ,  Kim Cheong Tang ,  Ajay Agarwal ,  Nagarajan Ranganathan

IPC分类号： G01N27/00 ,  G01N33/00 ,  B29B15/10

CPC分类号： G01N33/48728 ,  B01L3/5027

摘要： The present invention provides a device for analyzing the status of a biological entity. The device comprises a base substrate having a recess defined therein by two opposing lateral walls and a base wall, a filler member having at least a portion thereof occupying the recess, and a channel defined in the portion of the filler member occupying the recess, wherein the channel comprises a first aperture and a second aperture, the first aperture being arranged on a first lateral wall of the filler member, and the second aperture being arranged on a second lateral wall of the filler member, said first lateral wall of the filler member being arranged in opposing relationship with the second lateral wall of the filler member, and at least a portion of the first and the second lateral walls of the filler member being at least substantially perpendicular to the opposing lateral walls defining the recess.

摘要翻译： 本发明提供了一种用于分析生物实体的状态的装置。 该装置包括基底，其具有通过两个相对的侧壁和底壁限定的凹部，填充构件具有占据凹部的至少一部分，以及限定在占据凹部的填充构件的部分中的通道，其中 所述通道包括第一孔和第二孔，所述第一孔布置在所述填充构件的第一侧壁上，并且所述第二孔布置在所述填充构件的第二侧壁上，所述填充构件的所述第一侧壁 被布置成与填充构件的第二侧壁相对的关系，并且填充构件的第一和第二侧壁的至少一部分至少基本上垂直于限定凹部的相对侧壁。

公开(公告)号：US20090309627A1

公开(公告)日：2009-12-17

申请号：US12484708

申请日：2009-06-15

申请人： Nagarajan Ranganathan ,  Koustav Bhattacharya

发明人： Nagarajan Ranganathan ,  Koustav Bhattacharya

IPC分类号： H03K19/003 ,  H03K19/20 ,  H03K19/007

CPC分类号： H03K19/0033

摘要： The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.

摘要翻译： 本发明包括一种用于防止逻辑单元中软错误传播的电路级系统和方法。 当插入在逻辑单元的输出端时，包括RC微分器和耗尽型MOS电路的根据本发明的辐射干扰电路显着地减少了瞬态毛刺的传播。 辐射干扰电路是一种新颖的晶体管级优化技术，已被用于减少逻辑电路中的软错误。 还介绍了在延迟，功率和面积方面在放大器的逻辑电路中的选择节点上插入辐射干扰信号的方法。

公开(公告)号：US20070007996A1

公开(公告)日：2007-01-11

申请号：US11422973

申请日：2006-06-08

申请人： Nagarajan Ranganathan ,  Narender Hanchate

发明人： Nagarajan Ranganathan ,  Narender Hanchate

IPC分类号： H03K19/003

CPC分类号： H03K19/00361 ,  H03K17/162 ,  H03K17/6872 ,  H03K19/0013 ,  H03K2217/0036

摘要： An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.

摘要翻译： 描述了根据本发明的有效设计方法，用于减少CMOS电路中的泄漏功率。 根据本发明的方法和装置随着阈值电压的降低而产生更好的泄漏减少，从而有助于进一步降低电源电压并最小化晶体管尺寸。 与其他泄漏控制技术不同，本发明的技术不需要任何控制电路来监测电路的状态。 因此，避免以附加电路消耗的动态功率的形式牺牲获得的泄漏功率降低以控制整体电路状态。

公开(公告)号：US20180211033A1

公开(公告)日：2018-07-26

申请号：US15881020

申请日：2018-01-26

申请人： Santosh K. Aditham ,  Nagarajan Ranganathan

发明人： Santosh K. Aditham ,  Nagarajan Ranganathan

IPC分类号： G06F21/52

CPC分类号： G06F21/52 ,  G06F21/316 ,  G06F21/552 ,  G06F21/57 ,  G06F2221/034

摘要： A runtime attack can be detected on a big data system while processes are executed on various computing devices. A behavior profile can be maintained for tasks or processes running on different computing devices. The existence of a call variance in one of the traces for one of the behavior profiles can be determined. A memory variance can also be detected in one of the behavior profiles. A runtime attack has occurred when both the memory variance and the call variance are determined to exist.

公开(公告)号：US09531384B1

公开(公告)日：2016-12-27

申请号：US14955898

申请日：2015-12-01

申请人： Matthew Morrison ,  Jarred Adam Ligatti ,  Nagarajan Ranganathan

发明人： Matthew Morrison ,  Jarred Adam Ligatti ,  Nagarajan Ranganathan

IPC分类号： H03K19/00 ,  H03K19/003

CPC分类号： H03K19/0019 ,  H03K19/00315

摘要： An adiabatic dynamic differential logic circuit is provided for mitigating a differential power analysis (DPA) attack on a secure integrated chip including a plurality of transistors configured to perform each of a plurality of two-input logical output calculations, wherein each of the two-input logical output calculations results in a minimal differential power of the logic circuit. In one embodiment, a high-performance adiabatic dynamic differential logic circuit is provided which is optimized for very high operating frequencies. In another embodiment, a body-biased adiabatic dynamic differential logic circuit is provided which utilizes transistor body biasing to improve the switching time and differential power of the design.

摘要翻译： 提供一种绝热动态差分逻辑电路，用于减轻安全集成芯片上的差分功率分析（DPA）攻击，该安全集成芯片包括配置为执行多个双输入逻辑输出计算中的每一个的多个晶体管，其中每个双输入 逻辑输出计算导致逻辑电路的最小差分功率。 在一个实施例中，提供了一种针对非常高的工作频率进行了优化的高性能绝热动态差分逻辑电路。 在另一个实施例中，提供了体偏置的绝热动态差分逻辑电路，其利用晶体管体偏置来改善设计的开关时间和差动功率。

公开(公告)号：US20100187682A1

公开(公告)日：2010-07-29

申请号：US12442192

申请日：2007-09-21

申请人： Damaruganath Pinjala ,  Navas Khan Oratti Kalandar ,  Hengyun Zhang ,  Ebin Liao ,  Qingxin Zhang ,  Nagarajan Ranganathan ,  Vaidyanathan Kripesh

发明人： Damaruganath Pinjala ,  Navas Khan Oratti Kalandar ,  Hengyun Zhang ,  Ebin Liao ,  Qingxin Zhang ,  Nagarajan Ranganathan ,  Vaidyanathan Kripesh

IPC分类号： H01L23/46 ,  H01L21/02

CPC分类号： H01L23/473 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1627 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic package (200) comprises a substrate (201), a first carrier layer arrangement (211) adapted to dissipate heat from at least one chip (217) mounted thereon, and a heat exchanger (221) mounted on the first carrier layer arrangement. The first carrier layer arrangement comprises at least one internal microchannel (213), which is fluidically interconnected with the heat exchanger (221) though an inlet (215) and an outlet (219). The heat exchange further comprises a pump (223) controlling fluid flow through the microchannel (213). The package may further comprise a stack of carrier layer arrangements (211), each of which may have one or more chips (217) mounted thereon.

摘要翻译： 电子封装（200）包括衬底（201），适于从安装在其上的至少一个芯片（217）散发热量的第一载体层布置（211）和安装在第一载体层布置上的热交换器（221） 。 第一载体层布置包括至少一个内部微通道（213），其通过入口（215）和出口（219）与热交换器（221）流体地互连。 热交换器还包括控制流过微通道（213）的流体的泵（223）。 该封装还可以包括一叠载体层布置（211），每个载体层布置可以具有安装在其上的一个或多个芯片（217）。