公开(公告)号：US11328976B1

公开(公告)日：2022-05-10

申请号：US16808023

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Hoa Lap Do ,  Anthony Torza ,  Brian D. Philofsky

IPC: H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L23/42

Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

公开(公告)号：US10262920B1

公开(公告)日：2019-04-16

申请号：US15369607

申请日：2016-12-05

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/22 ,  H01L23/24 ,  H01L23/427 ,  H01L23/055 ,  H01L23/367 ,  H01L23/10

Abstract: Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die.

公开(公告)号：US11950358B1

公开(公告)日：2024-04-02

申请号：US17357089

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： Frank Peter Lambrecht ,  Brian D. Philofsky ,  Hong Shi ,  Prasun Raha

IPC: H05K1/02

CPC classification number: H05K1/0262

Abstract: A semiconductor device system comprises an integrated circuit (IC) die. The IC die is configured to operate in a first operating mode during a first period, and a second operating mode during a second period. The first period is associated with enabling an element of the IC die and a first amount of voltage droop. The second period occurs after the first period and is associated with a second amount of voltage droop. The second amount of voltage droop is less than the first amount of voltage droop.

公开(公告)号：US10147664B2

公开(公告)日：2018-12-04

申请号：US15495720

申请日：2017-04-24

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Daniel Elftmann ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H05K1/18 ,  H01L23/433 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

公开(公告)号：US20180308783A1

公开(公告)日：2018-10-25

申请号：US15495720

申请日：2017-04-24

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Daniel Elftmann ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/367 ,  H05K1/18 ,  H01L23/433 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/3672 ,  H01L23/3736 ,  H01L23/433 ,  H01L23/4338 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/72 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29293 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32221 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/0665 ,  H01L2924/01006

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

公开(公告)号：US09812374B1

公开(公告)日：2017-11-07

申请号：US15466495

申请日：2017-03-22

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Brian D. Philofsky

IPC: H01L23/12 ,  H01L21/00 ,  H05K7/20 ,  H01L23/367 ,  H01L23/427 ,  H01L25/065 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L23/10 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/427 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/292 ,  H01L2224/29224 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a device with a textured surface having multiple grooves in an otherwise relatively flat surface. The textured surface of the heat management device is designed, in conjunction with a thermal interface material (TIM), to push gas bubbles out of the flat areas such that the gas bubbles are trapped in the grooves or driven out of the interface between the device and the TIM altogether. The area of the grooves is small relative to the ungrooved areas (i.e., the flat areas), such that when the gas bubbles are trapped in the grooved areas, the ungrooved areas work even better for heat transfer. With the area of the regions for the flat portions being substantially greater than the area of the regions for the grooves, the textured heat management device is designed to lower thermal resistance, increase thermal conductivity, and increase heat transfer from one or more IC dies to a heat sink assembly in an IC package.