公开(公告)号：US20170077158A1

公开(公告)日：2017-03-16

申请号：US15258594

申请日：2016-09-07

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yi-Ming CHANG ,  Hsin KUAN

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14685 ,  H01L2224/11

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.

Abstract translation: 提供了包括基板的芯片封装。 基板具有与其相对的第一表面和第二表面。 衬底包括感测区域。 盖板在第一表面上并覆盖感测区域。 屏蔽层覆盖盖板的侧壁并朝向第二表面延伸。 屏蔽层具有与盖板相邻的内表面，并具有远离盖板的外表面。 朝向第二表面延伸的外表面的长度小于朝向第二表面延伸的内表面的长度，并且不小于盖板的侧壁的长度。 还提供了一种形成芯片封装的方法。

公开(公告)号：US20190140012A1

公开(公告)日：2019-05-09

申请号：US16178483

申请日：2018-11-01

Applicant: XINTEC INC.

Inventor： Hsin KUAN ,  Shih-Kuang CHEN ,  Chin-Ching HUANG ,  Chia-Ming CHENG

IPC: H01L27/146 ,  H01L23/00 ,  H01L21/56

Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.

公开(公告)号：US20150214162A1

公开(公告)日：2015-07-30

申请号：US14604525

申请日：2015-01-23

Applicant: XINTEC INC.

Inventor： Jiun-Yen LAI ,  Yu-Wen HU ,  Bai-Yao LOU ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Hsin KUAN

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03902 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

Abstract translation: 无源元件结构的制造方法包括以下步骤。 保护层形成在基板上，并且基板的接合焊盘分别通过保护层开口露出。 在接合焊盘和保护层上形成导电层。 在导电层上形成图案化的光致抗蚀剂层，并且与保护层开口相邻的导电层通过光致抗蚀剂层开口露出。 铜凸块分别电镀在导电层上。 除去未被铜凸块覆盖的光致抗蚀剂层和导电层。 在铜凸块和保护层上形成钝化层，并通过钝化层开口露出至少一个铜凸块。 扩散阻挡层和氧化阻挡层依次化学镀在铜凸块上。

公开(公告)号：US20170330871A1

公开(公告)日：2017-11-16

申请号：US15590302

申请日：2017-05-09

Applicant: XINTEC INC.

Inventor： Hsin KUAN ,  Chin-Ching HUANG ,  Chia-Ming CHENG

IPC: H01L25/16 ,  H01L31/0203 ,  H01L25/00

CPC classification number: H01L25/167 ,  H01L24/19 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/37001

Abstract: A chip package includes a sensing chip, a computing chip, and a protective layer annularly surrounding the sensing chip and the computing chip. The sensing chip has a first conductive pad, a sensing element, a first surface and a second surface opposite to each other. And the sensing element is disposed on the first surface. The computing chip has a second conductive pad and a computing element. The protective layer is formed by lamination and at least exposes the sensing element. The chip package further includes a conductive layer underneath the second surface of the sensing chip and extending to be in contact with the first conductive pad and the second conductive pad.

公开(公告)号：US20170092607A1

公开(公告)日：2017-03-30

申请号：US15272297

申请日：2016-09-21

Applicant: XINTEC INC.

Inventor： Hsin KUAN ,  Tsang-Yu LIU ,  Po-Han LEE

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/09 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A chip package is provided. The chip package includes a first substrate including a sensing region or device region. The chip package also includes a second substrate. The first substrate is mounted on the second substrate and is electrically connected to the second substrate. The ratio of the thickness of the first substrate to the thickness of the second substrate is in a range from 2 to 8.