公开(公告)号：US20170092619A1

公开(公告)日：2017-03-30

申请号：US14867349

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC: H01L25/065 ,  H01L23/06 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L23/10 ,  H01L23/367

CPC classification number: H01L23/373 ,  H01L21/4882 ,  H01L23/04 ,  H01L23/16 ,  H01L23/367 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US10529645B2

公开(公告)日：2020-01-07

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

公开(公告)号：US10043730B2

公开(公告)日：2018-08-07

申请号：US14867349

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC: H01L23/10 ,  H01L23/367 ,  H01L25/065 ,  H01L23/373 ,  H01L25/00 ,  H01L23/16 ,  H01L25/18 ,  H01L23/04 ,  H01L23/473 ,  H01L21/48 ,  H01L23/00 ,  H01L23/40

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US20240329329A1

公开(公告)日：2024-10-03

申请号：US18129765

申请日：2023-03-31

Applicant: XILINX, INC.

Inventor： Gamal REFAI-AHMED ,  Chuan Xie ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Nagadeven Karunakaran ,  Ferdinand F. Fernandez

IPC: G02B6/38 ,  G02B6/42

CPC classification number: G02B6/3849 ,  G02B6/381 ,  G02B6/4295

Abstract: A method of fabricating a chip package is provided, and a chip package fabricated using the same are provided. The method includes connecting a photonic die to a substrate of the chip package and attaching a protection apparatus to the substrate. The method also includes attaching a photonic connector to the photonic die. At least a portion of the photonic connector is disposed inside a housing of the protection apparatus. A fabrication process is performed on the chip package while the photonic connector is inside the housing. After processing, the photonic connector is removed from the housing.

公开(公告)号：US20180358280A1

公开(公告)日：2018-12-13

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.