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    Methods for fabricating FinFET integrated circuits in bulk semiconductor substrates
    3.
    发明授权
    Methods for fabricating FinFET integrated circuits in bulk semiconductor substrates 有权
    在半导体衬底中制造FinFET集成电路的方法

    公开(公告)号：US08461008B2

    公开(公告)日：2013-06-11

    申请号：US13210086

    申请日：2011-08-15

    申请人： Jin Cho

    发明人： Jin Cho

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823431 ,  H01L21/76224 ,  H01L29/66545

    摘要： Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas.

    摘要翻译： 提供了用于制造FinFET的方法，其避免了晶片或衬底上的厚度均匀性问题。 一种方法包括提供划分成多个芯片的半导体衬底，每个芯片由划线限定。 蚀刻基板以形成多个翅片，每个翅片均匀地延伸穿过芯片的宽度。 沉积氧化物以填充在翅片之间并且被蚀刻以使在该翅片顶部下方的氧化物的顶部凹陷。 隔离硬掩模被沉积并且图案覆盖在多个翅片上，并且被用作蚀刻掩模以蚀刻限定多个有效区域的衬底中的沟槽，所述多个有效区域中的每一个包括至少一部分至少一个 翅片 沟槽填充绝缘材料以隔离相邻的活性区域。

    MEMORY DEVICE AND METHOD THEREOF
    4.
    发明申请
    MEMORY DEVICE AND METHOD THEREOF 有权
    存储器件及其方法

    公开(公告)号：US20100146330A1

    公开(公告)日：2010-06-10

    申请号：US12330012

    申请日：2008-12-08

    申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

    发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

    IPC分类号： G06F11/20

    CPC分类号： G06F11/1048 ,  G11C2029/0411

    摘要： An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.

    摘要翻译： 公开了一种误差校正模块，其中两个比特单元用于以冗余的方式存储一位信息，使得冗余纠错模块可以校正两个比特之一的零星数据错误。

    Server system for performing communication over wireless network and communication method thereof
    6.
    发明申请
    Server system for performing communication over wireless network and communication method thereof 有权
    用于通过无线网络进行通信的服务器系统及其通信方法

    公开(公告)号：US20050125713A1

    公开(公告)日：2005-06-09

    申请号：US10896848

    申请日：2004-07-23

    申请人： Young Roh ,  Jung Kim ,  Jin Cho ,  Jae Chang ,  Sang Kang ,  Sang Kim ,  Pan Kim ,  Kwang Hong

    发明人： Young Roh ,  Jung Kim ,  Jin Cho ,  Jae Chang ,  Sang Kang ,  Sang Kim ,  Pan Kim ,  Kwang Hong

    IPC分类号： H04L12/26 ,  G08C25/02 ,  H04L1/00 ,  H04L1/08 ,  H04L1/18 ,  H04L12/00 ,  H04Q7/30

    CPC分类号： H04L1/18 ,  H04L1/0002

    摘要： Disclosed are a server system for performing communication over a wireless network and a communication method thereof. The server system comprises at least one client device and a server device for performing a state monitoring operation or a control operation for the client device over the wireless network. When a data packet is sent, the server device begins to send a following packet by variably applying a transmission rate according to a network transmission state when a leading packet has been completely transmitted. Because a transmission rate can be set appropriately to the network state, the number of unnecessary retransmissions can be reduced. Therefore, transmission delay can be avoided and stable and rapid wireless communication can be achieved.

    摘要翻译： 公开了一种通过无线网络进行通信的服务器系统及其通信方法。 服务器系统包括至少一个客户端设备和服务器设备，用于通过无线网络对客户端设备执行状态监视操作或控制操作。 当发送数据分组时，当前导分组被完全发送时，服务器设备开始通过可变地应用根据网络传输状态的传输速率发送后续分组。 因为可以适当地设置传输速率到网络状态，所以可以减少不必要的重发次数。 因此，可以避免传输延迟，实现稳定快速的无线通信。

    Methods of forming a dielectric cap layer on a metal gate structure
    7.
    发明授权
    Methods of forming a dielectric cap layer on a metal gate structure 有权
    在金属栅极结构上形成电介质盖层的方法

    公开(公告)号：US09117877B2

    公开(公告)日：2015-08-25

    申请号：US13350908

    申请日：2012-01-16

    申请人： Xiuyu Cai ,  Ruilong Xie ,  Jin Cho ,  John Iacoponi

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Jin Cho ,  John Iacoponi

    IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/785 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

    摘要： Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.

    摘要翻译： 本文公开了在FinFET和其它半导体器件上形成隔离结构的各种方法，以及具有这种隔离结构的所得器件。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于FinFET器件的鳍片，在沟槽中形成绝缘材料层，其中绝缘材料层覆盖下部 翅片的一部分而不是翅片的上部，在翅片的上部形成保护材料，并且在氧化环境中进行加热处理，以在翅片的被覆盖的下部形成热氧化物区域。

    Methods for fabricating integrated circuits
    8.
    发明授权
    Methods for fabricating integrated circuits 有权
    集成电路的制造方法

    公开(公告)号：US08853037B2

    公开(公告)日：2014-10-07

    申请号：US13420412

    申请日：2012-03-14

    申请人： Jin Cho

    发明人： Jin Cho

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/823431 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    摘要： Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A plurality of trenches is etched into the first and second layers. Portions of the second layer that are disposed between the plurality of trenches define a plurality of fins. A gate structure is formed overlying the plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is at least partially supported in position adjacent to the gap spaces by the gate structure. The gap spaces are filled with an insulating material.

    摘要翻译： 提供了形成半导体器件的方法。 一种方法包括形成覆盖体半导体衬底的第一层。 第二层形成在第一层上。 多个沟槽被蚀刻到第一层和第二层中。 设置在多个沟槽之间的第二层的部分限定多个鳍。 形成在多个翅片上的栅极结构。 蚀刻第一层以在体半导体衬底和多个鳍之间形成间隙。 多个鳍片通过栅极结构至少部分地支撑在与间隙空间相邻的位置。 间隙空间填充绝缘材料。

    METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME
    9.
    发明申请
    METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME 有权
    使用本地互连处理方案形成半导体器件的联系方法

    公开(公告)号：US20130295756A1

    公开(公告)日：2013-11-07

    申请号：US13465633

    申请日：2012-05-07

    申请人： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

    发明人： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

    IPC分类号： H01L21/28 ,  H01L21/283

    CPC分类号： H01L21/823475 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

    摘要翻译： 本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触，其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构 并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域，并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层 的局部互连结构位于分离第一和第二有源区域的隔离区域之上。 该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分，从而限定位于局部互连结构的剩余部分上方的凹槽，以及在凹部中形成绝缘材料。

    Methods of Forming a Replacement Gate Comprised of Silicon and a Device Including Same
    10.
    发明申请
    Methods of Forming a Replacement Gate Comprised of Silicon and a Device Including Same 审中-公开
    形成由硅和包括其的器件组成的替代栅极的方法

    公开(公告)号：US20130043592A1

    公开(公告)日：2013-02-21

    申请号：US13213449

    申请日：2011-08-19

    申请人： Chang Seo Park ,  Jin Cho

    发明人： Chang Seo Park ,  Jin Cho

    IPC分类号： H01L29/49 ,  H01L21/28

    CPC分类号： H01L29/4966 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/7833

    摘要： Disclosed herein are various methods of forming a replacement gate comprised of silicon and various semiconductor devices incorporation such a replacement gate structure. In one example, the method includes removing a sacrificial gate electrode structure to define a gate opening, forming a replacement gate structure in the gate opening, the replacement gate structure including at least one metal layer and a silicon-containing gate structure that is at least partially made of a metal silicide and forming a protective layer above at least a portion of the replacement gate structure.

    摘要翻译： 本文公开了形成由硅构成的替代栅极和结合这种替代栅极结构的各种半导体器件的各种方法。 在一个示例中，该方法包括去除牺牲栅极电极结构以限定栅极开口，在栅极开口中形成替代栅极结构，所述替换栅极结构至少包括一个金属层和至少含有硅的栅极结构 部分地由金属硅化物制成并在替代栅极结构的至少一部分上方形成保护层。