公开(公告)号：US08455346B2

公开(公告)日：2013-06-04

申请号：US13075658

申请日：2011-03-30

申请人： Yasuhiro Nojiri ,  Hiroyuki Fukumizu ,  Shinichi Nakao ,  Kei Watanabe ,  Kazuhiko Yamamoto ,  Ichiro Mizushima ,  Yoshio Ozawa

发明人： Yasuhiro Nojiri ,  Hiroyuki Fukumizu ,  Shinichi Nakao ,  Kei Watanabe ,  Kazuhiko Yamamoto ,  Ichiro Mizushima ,  Yoshio Ozawa

IPC分类号： H01L21/4763 ,  G11C11/00

CPC分类号： H01L51/0591 ,  B82Y10/00 ,  B82Y40/00 ,  G11C13/0002 ,  G11C13/025 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/149 ,  H01L45/1608

摘要： According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.

摘要翻译： 根据一个实施例，公开了一种用于制造非易失性存储器件的方法。 非易失性存储器件包括连接到第一互连和第二互连的存储单元。 该方法可以包括在第一互连上形成第一电极膜。 该方法可以包括在第一电极膜上形成分散在绝缘体内的多个碳纳米管的层。 多个碳纳米管中的至少一个碳纳米管从绝缘体的表面露出。 该方法可以包括在该层上形成第二电极膜。 此外，该方法可以包括在第二电极膜上形成第二互连。

公开(公告)号：US20110306199A1

公开(公告)日：2011-12-15

申请号：US13075658

申请日：2011-03-30

申请人： Yasuhiro NOJIRI ,  Hiroyuki Fukumizu ,  Shinichi Nakao ,  Kei Watanabe ,  Kazuhiko Yamamoto ,  Ichiro Mizushima ,  Yoshio Ozawa

发明人： Yasuhiro NOJIRI ,  Hiroyuki Fukumizu ,  Shinichi Nakao ,  Kei Watanabe ,  Kazuhiko Yamamoto ,  Ichiro Mizushima ,  Yoshio Ozawa

IPC分类号： H01L21/768 ,  B82Y99/00

CPC分类号： H01L51/0591 ,  B82Y10/00 ,  B82Y40/00 ,  G11C13/0002 ,  G11C13/025 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/149 ,  H01L45/1608

摘要： According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.

摘要翻译： 根据一个实施例，公开了一种用于制造非易失性存储器件的方法。 非易失性存储器件包括连接到第一互连和第二互连的存储单元。 该方法可以包括在第一互连上形成第一电极膜。 该方法可以包括在第一电极膜上形成分散在绝缘体内的多个碳纳米管的层。 多个碳纳米管中的至少一个碳纳米管从绝缘体的表面露出。 该方法可以包括在该层上形成第二电极膜。 此外，该方法可以包括在第二电极膜上形成第二互连。

公开(公告)号：US20120119179A1

公开(公告)日：2012-05-17

申请号：US13354380

申请日：2012-01-20

申请人： Shinichi Nakao ,  Kei Watanabe ,  Kazuhiko Yamamoto ,  Ichiro Mizushima ,  Yoshio Ozawa

发明人： Shinichi Nakao ,  Kei Watanabe ,  Kazuhiko Yamamoto ,  Ichiro Mizushima ,  Yoshio Ozawa

IPC分类号： H01L47/00 ,  H01L21/02 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： B82Y10/00 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/149 ,  H01L45/1608

摘要： According to one embodiment, a memory device includes a nanomaterial aggregate layer of a plurality of fine conductors aggregating via gaps and an insulating material disposed in the gaps.

摘要翻译： 根据一个实施例，存储器件包括通过间隙聚集的多个细小导体的纳米材料聚集体层和设置在间隙中的绝缘材料。

公开(公告)号：US20120217464A1

公开(公告)日：2012-08-30

申请号：US13404678

申请日：2012-02-24

申请人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

发明人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/149

摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.

摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。

公开(公告)号：US20120205609A1

公开(公告)日：2012-08-16

申请号：US13235842

申请日：2011-09-19

申请人： Shigeto OSHINO ,  Kenji Aoyama ,  Kazuhiko Yamamoto ,  Shinichi Nakao ,  Kei Watanabe ,  Satoshi Ishikawa

发明人： Shigeto OSHINO ,  Kenji Aoyama ,  Kazuhiko Yamamoto ,  Shinichi Nakao ,  Kei Watanabe ,  Satoshi Ishikawa

IPC分类号： H01L45/00 ,  H01L21/8239 ,  B82Y99/00

CPC分类号： H01L27/101 ,  B82Y10/00 ,  B82Y30/00 ,  H01L27/2481 ,  H01L45/149 ,  H01L45/1608

摘要： According to one embodiment, a memory device includes a lower electrode layer, a nanomaterial assembly layer, a protective layer and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of fine conductors assembled via a gap. The protective layer is provided on the nanomaterial assembly layer, is conductive, is in contact with the fine conductors, and includes an opening. The upper electrode layer is provided on the protective layer and is in contact with the protective layer.

摘要翻译： 根据一个实施例，存储器件包括下电极层，纳米材料组合层，保护层和上电极层。 纳米材料组装层设置在下电极层上，并且包括通过间隙组装的多个细导体。 保护层设置在纳米材料组装层上，导电，与细导体接触，并包括开口。 上电极层设置在保护层上并与保护层接触。

公开(公告)号：US08895952B2

公开(公告)日：2014-11-25

申请号：US13404678

申请日：2012-02-24

申请人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

发明人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/149

摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.

摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。

公开(公告)号：US08772153B2

公开(公告)日：2014-07-08

申请号：US13423081

申请日：2012-03-16

申请人： Takashi Furuhashi ,  Miyoko Shimada ,  Ichiro Mizushima ,  Shinichi Nakao

发明人： Takashi Furuhashi ,  Miyoko Shimada ,  Ichiro Mizushima ,  Shinichi Nakao

IPC分类号： H01L21/4763 ,  H01L21/31 ,  H01L23/52 ,  H01L21/76

CPC分类号： H01L21/7682 ,  H01L21/31053 ,  H01L21/76834 ,  H01L21/76885

摘要： In accordance with an embodiment, a semiconductor device includes a substrate, a line-and-space structure, a first film and a second film. The line-and-space structure includes line patterns arranged on the substrate parallel to one another at a predetermined distance. The first film is formed on side surfaces and bottom surfaces of the line patterns by an insulating film material. The second film is formed on the line-and-space structure across a space between the line patterns by a material showing low wettability to the first film. Space between the line patterns includes an air gap in which at least a bottom surface of the first film is totally exposed.

摘要翻译： 根据实施例，半导体器件包括衬底，线间距结构，第一膜和第二膜。 线间空间结构包括以预定距离彼此平行布置在基板上的线图案。 第一膜通过绝缘膜材料形成在线图案的侧表面和底表面上。 通过对第一膜显示低润湿性的材料，在线图形之间的空间结构上形成第二膜。 线图案之间的空间包括其中至少第一膜的底表面完全暴露的气隙。

公开(公告)号：US20100181673A1

公开(公告)日：2010-07-22

申请号：US12652204

申请日：2010-01-05

申请人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US20130093090A1

公开(公告)日：2013-04-18

申请号：US13707359

申请日：2012-12-06

申请人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/485

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US08536706B2

公开(公告)日：2013-09-17

申请号：US13707359

申请日：2012-12-06

申请人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.