-
公开(公告)号：US08455346B2
公开(公告)日：2013-06-04
申请号：US13075658
申请日：2011-03-30
申请人： Yasuhiro Nojiri , Hiroyuki Fukumizu , Shinichi Nakao , Kei Watanabe , Kazuhiko Yamamoto , Ichiro Mizushima , Yoshio Ozawa
发明人： Yasuhiro Nojiri , Hiroyuki Fukumizu , Shinichi Nakao , Kei Watanabe , Kazuhiko Yamamoto , Ichiro Mizushima , Yoshio Ozawa
IPC分类号： H01L21/4763 , G11C11/00
CPC分类号： H01L51/0591 , B82Y10/00 , B82Y40/00 , G11C13/0002 , G11C13/025 , G11C2213/71 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/149 , H01L45/1608
摘要： According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.
摘要翻译： 根据一个实施例，公开了一种用于制造非易失性存储器件的方法。 非易失性存储器件包括连接到第一互连和第二互连的存储单元。 该方法可以包括在第一互连上形成第一电极膜。 该方法可以包括在第一电极膜上形成分散在绝缘体内的多个碳纳米管的层。 多个碳纳米管中的至少一个碳纳米管从绝缘体的表面露出。 该方法可以包括在该层上形成第二电极膜。 此外，该方法可以包括在第二电极膜上形成第二互连。
-
公开(公告)号：US20110306199A1
公开(公告)日：2011-12-15
申请号：US13075658
申请日：2011-03-30
申请人： Yasuhiro NOJIRI , Hiroyuki Fukumizu , Shinichi Nakao , Kei Watanabe , Kazuhiko Yamamoto , Ichiro Mizushima , Yoshio Ozawa
发明人： Yasuhiro NOJIRI , Hiroyuki Fukumizu , Shinichi Nakao , Kei Watanabe , Kazuhiko Yamamoto , Ichiro Mizushima , Yoshio Ozawa
IPC分类号： H01L21/768 , B82Y99/00
CPC分类号： H01L51/0591 , B82Y10/00 , B82Y40/00 , G11C13/0002 , G11C13/025 , G11C2213/71 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/149 , H01L45/1608
摘要： According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.
摘要翻译： 根据一个实施例，公开了一种用于制造非易失性存储器件的方法。 非易失性存储器件包括连接到第一互连和第二互连的存储单元。 该方法可以包括在第一互连上形成第一电极膜。 该方法可以包括在第一电极膜上形成分散在绝缘体内的多个碳纳米管的层。 多个碳纳米管中的至少一个碳纳米管从绝缘体的表面露出。 该方法可以包括在该层上形成第二电极膜。 此外，该方法可以包括在第二电极膜上形成第二互连。
-
公开(公告)号：US20120119179A1
公开(公告)日：2012-05-17
申请号：US13354380
申请日：2012-01-20
CPC分类号： B82Y10/00 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/149 , H01L45/1608
摘要： According to one embodiment, a memory device includes a nanomaterial aggregate layer of a plurality of fine conductors aggregating via gaps and an insulating material disposed in the gaps.
摘要翻译： 根据一个实施例，存储器件包括通过间隙聚集的多个细小导体的纳米材料聚集体层和设置在间隙中的绝缘材料。
-
公开(公告)号：US08378331B2
公开(公告)日：2013-02-19
申请号：US12707136
申请日：2010-02-17
申请人： Yasuhiro Satoh , Tsukasa Nakai , Kazuhiko Yamamoto , Motoya Kishida , Hiroyuki Fukumizu , Yasuhiro Nojiri
发明人： Yasuhiro Satoh , Tsukasa Nakai , Kazuhiko Yamamoto , Motoya Kishida , Hiroyuki Fukumizu , Yasuhiro Nojiri
IPC分类号： H01L29/02
CPC分类号： H01L45/1233 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/149 , H01L45/1641
摘要： This nonvolatile semiconductor memory device comprises a memory cell array including memory cells arranged therein. Each of the memory cells is located at respective intersections between first wirings and second wirings and includes a variable resistance element. The variable resistance element comprises a thin film including carbon (C). The thin film includes a side surface along a direction of a current flowing in the memory cell. The side surface includes carbon nitride (CNx).
摘要翻译： 该非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括布置在其中的存储单元。 每个存储单元位于第一布线和第二布线之间的相应交点处，并且包括可变电阻元件。 可变电阻元件包括包含碳（C）的薄膜。 薄膜包括沿着在存储单元中流动的电流的方向的侧表面。 侧表面包括碳氮化物（CNx）。
-
公开(公告)号：US20100237319A1
公开(公告)日：2010-09-23
申请号：US12707136
申请日：2010-02-17
申请人： Yasuhiro SATOH , Tsukasa Nakai , Kazuhiko Yamamoto , Motoya Kishida , Hiroyuki Fukumizu , Yasuhiro Nojiri
发明人： Yasuhiro SATOH , Tsukasa Nakai , Kazuhiko Yamamoto , Motoya Kishida , Hiroyuki Fukumizu , Yasuhiro Nojiri
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/149 , H01L45/1641
摘要： This nonvolatile semiconductor memory device comprises a memory cell array including memory cells arranged therein. Each of the memory cells is located at respective intersections between first wirings and second wirings and includes a variable resistance element. The variable resistance element comprises a thin film including carbon (C). The thin film includes a side surface along a direction of a current flowing in the memory cell. The side surface includes carbon nitride (CNx).
摘要翻译： 该非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括布置在其中的存储单元。 每个存储单元位于第一布线和第二布线之间的相应交点处，并且包括可变电阻元件。 可变电阻元件包括包含碳（C）的薄膜。 薄膜包括沿着在存储单元中流动的电流的方向的侧表面。 侧表面包括碳氮化物（CNx）。
-
公开(公告)号：US20110303888A1
公开(公告)日：2011-12-15
申请号：US13044865
申请日：2011-03-10
IPC分类号： H01L45/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/065 , H01L45/1233 , H01L45/1608 , H01L45/1675
摘要： According to one embodiment, a nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The memory cell includes a plurality of layers. The plurality of layers includes a carbon-containing memory layer sandwiched between a first electrode film and a second electrode film and a carbon-containing barrier layer provided at least one of between the first electrode film and the memory layer and between the second electrode film and the memory layer. The barrier layer has lower electrical resistivity than the memory layer.
摘要翻译： 根据一个实施例，非易失性存储器件包括连接到第一互连和第二互连的存储单元。 存储单元包括多个层。 多个层包括夹在第一电极膜和第二电极膜之间的含碳存储层和设置在第一电极膜和存储层之间以及第二电极膜和第二电极膜之间的至少一个的含碳阻挡层， 内存层。 阻挡层的电阻率比存储层低。
-
公开(公告)号：US20120205609A1
公开(公告)日：2012-08-16
申请号：US13235842
申请日：2011-09-19
申请人： Shigeto OSHINO , Kenji Aoyama , Kazuhiko Yamamoto , Shinichi Nakao , Kei Watanabe , Satoshi Ishikawa
发明人： Shigeto OSHINO , Kenji Aoyama , Kazuhiko Yamamoto , Shinichi Nakao , Kei Watanabe , Satoshi Ishikawa
IPC分类号： H01L45/00 , H01L21/8239 , B82Y99/00
CPC分类号： H01L27/101 , B82Y10/00 , B82Y30/00 , H01L27/2481 , H01L45/149 , H01L45/1608
摘要： According to one embodiment, a memory device includes a lower electrode layer, a nanomaterial assembly layer, a protective layer and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of fine conductors assembled via a gap. The protective layer is provided on the nanomaterial assembly layer, is conductive, is in contact with the fine conductors, and includes an opening. The upper electrode layer is provided on the protective layer and is in contact with the protective layer.
摘要翻译： 根据一个实施例，存储器件包括下电极层，纳米材料组合层，保护层和上电极层。 纳米材料组装层设置在下电极层上，并且包括通过间隙组装的多个细导体。 保护层设置在纳米材料组装层上，导电，与细导体接触，并包括开口。 上电极层设置在保护层上并与保护层接触。
-
公开(公告)号：US20120217464A1
公开(公告)日：2012-08-30
申请号：US13404678
申请日：2012-02-24
申请人： Shigeki Kobayashi , Kazuhiko Yamamoto , Kenji Aoyama , Shigeto Oshino , Kei Watanabe , Shinichi Nakao , Satoshi Ishikawa , Takeshi Yamaguchi
发明人： Shigeki Kobayashi , Kazuhiko Yamamoto , Kenji Aoyama , Shigeto Oshino , Kei Watanabe , Shinichi Nakao , Satoshi Ishikawa , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/149
摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.
摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。
-
公开(公告)号：US08895952B2
公开(公告)日：2014-11-25
申请号：US13404678
申请日：2012-02-24
申请人： Shigeki Kobayashi , Kazuhiko Yamamoto , Kenji Aoyama , Shigeto Oshino , Kei Watanabe , Shinichi Nakao , Satoshi Ishikawa , Takeshi Yamaguchi
发明人： Shigeki Kobayashi , Kazuhiko Yamamoto , Kenji Aoyama , Shigeto Oshino , Kei Watanabe , Shinichi Nakao , Satoshi Ishikawa , Takeshi Yamaguchi
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/149
摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.
摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。
-
公开(公告)号：US08866119B2
公开(公告)日：2014-10-21
申请号：US13051264
申请日：2011-03-18
申请人： Kazuhiko Yamamoto , Kenji Aoyama
发明人： Kazuhiko Yamamoto , Kenji Aoyama
CPC分类号： H01L45/04 , G11C13/0014 , G11C13/025 , G11C2213/16 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/1233 , H01L45/145 , H01L45/149 , H01L45/1675
摘要： According to one embodiment, a memory device includes a selection element layer, a nanomaterial aggregate layer, and a fine particle. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer has a plurality of micro conductive bodies aggregated with an interposed gap. The fine particle has at least a surface made of silicon oxynitride. The fine particle is dispersed between the micro conductive bodies in one portion of the nanomaterial aggregate layer piercing the nanomaterial aggregate layer in a thickness direction.
摘要翻译： 根据一个实施例，存储器件包括选择元件层，纳米材料聚集体层和细颗粒。 纳米材料聚集层层叠在选择元件层上。 纳米材料聚集体层具有多个与插入的间隙聚集的微导电体。 细颗粒至少具有由氮氧化硅制成的表面。 微细颗粒分散在纳米材料聚集体层的一部分中的微导电体之间，该纳米材料聚集体层在厚度方向上穿透纳米材料聚集体层。
-
-
-
-
-
-
-
-
-
搜索结果
118 条记录 (耗时 0.03 秒)