公开(公告)号：US06365828B1

公开(公告)日：2002-04-02

申请号：US09691257

申请日：2000-10-19

申请人： Yasushi Kinoshita ,  Hiroshi Wabuka ,  Shiro Yoshida ,  Hirokazu Tohya ,  Toru Mori ,  Atsushi Ochi

发明人： Yasushi Kinoshita ,  Hiroshi Wabuka ,  Shiro Yoshida ,  Hirokazu Tohya ,  Toru Mori ,  Atsushi Ochi

IPC分类号： H05K900

CPC分类号： H05K1/165 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/162 ,  H05K7/1092 ,  H05K9/0066 ,  H05K2201/1006 ,  H05K2201/10689 ,  H01L2924/00

摘要： The electromagnetic interference suppressing device of the present invention includes a plurality of connection layers and ground layers formed of a conductive material. The connection layers and the ground layers are alternately layered. Insulating layers, formed of an insulating material, intervene between the neighboring connection layers and ground layers. The odd connection layers counting from the bottom and the connection layers just above those layers are electrically connected at the same end. The even connection layers counting from the bottom and the connection layers just above those layers are electrically connected at the same end opposite to the odd connection-layered end. The bottommost connection layer is connected to a first signal terminal. The uppermost connection layer is connected to a second signal terminal. The ground layer is connected to a ground terminal.

摘要翻译： 本发明的电磁干扰抑制装置包括多个连接层和由导电材料形成的接地层。 连接层和接地层交替层叠。 由绝缘材料形成的绝缘层介于相邻连接层和接地层之间。 从底部计数的奇数连接层和正好在这些层上方的连接层在同一端电连接。 从底部开始计数的连接层和刚好在这些层上方的连接层在与奇数连接分层端相反的相同端部电连接。 最下面的连接层连接到第一信号端子。 最上面的连接层连接到第二信号端子。 接地层连接到接地端子。

公开(公告)号：US06477694B1

公开(公告)日：2002-11-05

申请号：US09698588

申请日：2000-10-27

申请人： Hitoshi Irino ,  Noriaki Ando ,  Hiroshi Wabuka ,  Hirokazu Tohya

发明人： Hitoshi Irino ,  Noriaki Ando ,  Hiroshi Wabuka ,  Hirokazu Tohya

IPC分类号： G06F1750

CPC分类号： H05K1/0231 ,  G06F17/5068 ,  H05K1/165 ,  H05K3/0005 ,  H05K2201/10689

摘要： A design support system 100 according to the present invention comprises: an LSI library 10, in which rated characteristics of various LSIs are stored by an LSI library preparation unit 70; a decoupling capacitor library 20, in which rated characteristics of various capacitors are stored; a PCB library 30, in which the cross-sectional structures of various power wiring lines are stored; a decoupling capacitor search unit 40, for employing the LSI library 10 and the decoupling capacitor library 20; a power wiring determination unit 50, for employing the results obtained by the decoupling capacitor search unit 40, the LSI library 10 and the PCB library 30; and a design results output unit 60, for outputting the results received from the power wiring determination unit 50. Furthermore, the data in the three libraries can be updated or new data can be added.

摘要翻译： 根据本发明的设计支持系统100包括：LSI库10，其中LSI库准备单元70存储各种LSI的额定特性; 去耦电容器库20，其中存储各种电容器的额定特性; PCB库30，其中存储各种电力布线的横截面结构; 去耦电容器搜索单元40，用于采用LSI库10和去耦电容器库20; 电源布线确定单元50，用于采用由去耦电容器搜索单元40，LSI库10和PCB库30获得的结果; 以及设计结果输出单元60，用于输出从电力布线确定单元50接收的结果。此外，可以更新三个库中的数据或者可以添加新的数据。

公开(公告)号：US06550037B2

公开(公告)日：2003-04-15

申请号：US09729852

申请日：2000-12-06

申请人： Noriaki Ando ,  Hitoshi Irino ,  Hiroshi Wabuka ,  Hirokazu Tohya

发明人： Noriaki Ando ,  Hitoshi Irino ,  Hiroshi Wabuka ,  Hirokazu Tohya

IPC分类号： G06F1750

CPC分类号： H05K3/0005 ,  G06F17/5068 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/10689

摘要： A method for designing a decoupling circuit for a source line of a LSI includes the steps of determining the capacitance of the decoupling capacitor based on the electric charge necessary for one cycle operation of the LSI and the allowable fluctuation of the source voltage, and determining the inductance of the source line based on the impedance of the decoupling capacitor and the allowable minimum multiplexing ratio of the source current by the decoupling capacitor.

摘要翻译： 设计用于LSI的源极线的去耦电路的方法包括以下步骤：基于LSI的一个周期操作所需的电荷和源极电压的允许波动来确定去耦电容器的电容，并且确定 基于去耦电容器的阻抗的源极线的电感和去耦电容器的源电流的允许的最小复用比。

公开(公告)号：US06359237B1

公开(公告)日：2002-03-19

申请号：US09637684

申请日：2000-08-14

申请人： Hirokazu Tohya ,  Shiro Yoshida

发明人： Hirokazu Tohya ,  Shiro Yoshida

IPC分类号： H01R909

CPC分类号： H05K1/0248 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09263 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/10689

摘要： In order to reduce electromagnetic inductive interference due to power source current, in a multi-layer printed board on which a multiplicity of high-speed and high-frequency circuit elements are mounted, a multi-layer printed board has a construction such that on both upper and lower sides of a power source layer 1 provided with power source wiring 6, are laminated ground layers 2 via respective first insulating material layers 4, and on one or both of the upper and lower sides of these is laminated a signal layer 3 provided with signal wiring, via a second insulating material layer 5.

摘要翻译： 为了减少由于电源电流引起的电磁感应干扰，在多层印刷电路板上安装有多个高速和高频电路元件的情况下，多层印刷电路板具有这样的结构： 设置有电源布线6的电源层1的上侧和下侧经由各自的第一绝缘材料层4层叠接地层2，并且在它们的上侧和下侧的一侧或两侧层叠有提供的信号层3 具有信号线，经由第二绝缘材料层5。

公开(公告)号：US07064623B2

公开(公告)日：2006-06-20

申请号：US10476843

申请日：2002-04-25

申请人： Shiro Yoshida ,  Hirokazu Tohya ,  Masayuki Shimizu

发明人： Shiro Yoshida ,  Hirokazu Tohya ,  Masayuki Shimizu

IPC分类号： H03H7/01

CPC分类号： H01P1/202 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01P3/06 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/0298 ,  H05K2201/09809 ,  H05K2201/10287 ,  H01L2924/00 ,  H01L2924/00014

摘要： Transmission line type components (1, 1′), which form coaxial lines having a very low characteristic impedance by coaxially installing a cylindrical outer conductor made of a conductive material being larger in diameter than an inner conductor so as to cover via a high dielectric insulating material the surface of an inner conductor made of a conductive material, are inserted in series between a power supply line (8) and a ground line (9) connected with a dc source on a printed circuit board and an I.SI (6) power supply port, whereby almost the entire high-frequency power supply current generated from the I.SI (6) is reflected off the I.SI (6) power supply port, and part of the high-frequency power supply current intruding into the components (1, 1′) is consumed and does not reach the external power supply line (8).

摘要翻译： 传输线类型部件（1,1'）通过同轴地安装由导电材料制成的圆柱形外部导体形成具有非常低的特性阻抗的同轴线，其直径大于内部导体，以便经由高介电绝缘体 将由导电材料制成的内部导体的表面材料串联插入到与印刷电路板上的直流源连接的电源线（8）和接地线（9）之间.ISI（6） 电源端口，几乎从ISI（6）产生的整个高频电源电流都从ISI（6）电源端口反射出来，部分高频电源电流侵入 组件（1,1'）被消耗并且不到达外部电源线（8）。

公开(公告)号：US06938231B2

公开(公告)日：2005-08-30

申请号：US10469328

申请日：2002-02-26

申请人： Shiro Yoshida ,  Hirokazu Tohya

发明人： Shiro Yoshida ,  Hirokazu Tohya

IPC分类号： G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A circuit layout design method capable of an LSI circuit or an electronic printed circuit board free of electromagnetic interference is provided. The layout design method according to the invention includes a quasi-stationary circuit reduction step of deviding an entire circuit represented by a net list and a part library into a plurality of quasi-stationary closed circuits having a reduced size so that an intensity of an electromagnetic wave radiated from each of the quasi-stationary closed circuits is not more than a predetermined value; a wiring constraint condition calculation step of calculating constraint conditions for each of wirings mutually connecting the plurality of quasi-stationary closed circuits so that the intensity of the electromagnetic wave radiated from each of the wirings is not more than the predetermined value; and a layout step of laying out parts and the wirings based on the net list and the parts library so as to satisfy the constraint conditions.

摘要翻译： 提供一种能够进行LSI电路或无电磁干扰的电子印刷电路板的电路布局设计方法。 根据本发明的布局设计方法包括准稳定电路减少步骤，将由网表和部件库表示的整个电路分离成具有减小的尺寸的多个准静态闭合电路，使得电磁 从每个准静态闭合电路辐射的波形不大于预定值; 布线约束条件计算步骤，计算相互连接所述多个准静止闭合电路的每个布线的约束条件，使得从所述布线辐射的电磁波的强度不大于所述预定值; 以及基于网表和零件库布局零件和布线以便满足约束条件的布局步骤。

公开(公告)号：US6075211A

公开(公告)日：2000-06-13

申请号：US713619

申请日：1996-09-13

申请人： Hirokazu Tohya ,  Shiro Yoshida

发明人： Hirokazu Tohya ,  Shiro Yoshida

IPC分类号： H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/16 ,  H05K3/46

CPC分类号： H05K1/0233 ,  H05K1/165 ,  H05K1/0298 ,  H05K1/0373 ,  H05K2201/0191 ,  H05K2201/086 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/10015 ,  H05K2201/10689 ,  H05K3/4688

摘要： There is provided a multi-layered printed wiring board including a power supply layer, a ground layer, a signal layer, and insulators sandwiched between those layers. The power supply layer is provided with a circuit in the form of wirings for imparting impedance thereto. For instance, the power supply layer may be formed to include main wirings for distributing a dc current entirely to the printed wiring board with a dc voltage drop being depressed, and branch wirings for enhancing high frequency impedance to isolate circuits in terms of high frequency, which circuits are mounted on the multi-layered printed wiring board and operated independently with each other. The invention makes it possible to provide a relatively great inductance to thereby decrease high frequency power supply current which is generated on IC/LSI operation and is to flow into decoupling capacitors. In addition, in accordance with the present invention, it is possible to identify a route through which a current runs into the power supply layer to thereby provide an optimal decoupling capacitor to every IC/LSI as a source of high frequency power supply current.

摘要翻译： 提供了一种多层印刷布线板，其包括电源层，接地层，信号层和夹在这些层之间的绝缘体。 电源层设置有用于赋予阻抗的布线形式的电路。 例如，电源层可以形成为包括用于将直流电流全部分配到具有直流电压降的印刷电路板的主布线，以及用于增强高频阻抗的分支布线以隔离高频率的电路， 哪些电路安装在多层印刷电路板上并彼此独立地操作。 本发明使得可以提供相当大的电感，从而降低在IC / LSI操作时产生的高频电源电流并且流入去耦电容器。 此外，根据本发明，可以识别电流流入电源层的路径，从而为作为高频电源电流源的每个IC / LSI提供最佳去耦电容。

公开(公告)号：US6111479A

公开(公告)日：2000-08-29

申请号：US33554

申请日：1998-03-02

申请人： Osamu Myohga ,  Shiro Yoshida ,  Mitsuo Saito ,  Yuzo Shimada ,  Hirokazu Tohya ,  Ryo Maniwa

发明人： Osamu Myohga ,  Shiro Yoshida ,  Mitsuo Saito ,  Yuzo Shimada ,  Hirokazu Tohya ,  Ryo Maniwa

IPC分类号： H05K9/00 ,  H03H7/01 ,  H05K1/00 ,  H05K1/02 ,  H05K3/46

CPC分类号： H05K1/0233 ,  H03H7/01 ,  H05K1/0216 ,  H05K1/0298

摘要： A laminate printed circuit board loaded with transistors, ICs (Integrated Circuits) or LSIs (Large Scale Integrated Circuits) and a method of producing the same are disclosed. The circuit board includes a signal layer, a ground layer and a power supply layer sequentially laminated with the intermediary of insulation layers. An impedance adding circuit is formed in the power supply layer. A magnetic layer is positioned at least above or at least blow the impedance adding circuit. The circuit board with this configuration reduces power supply noise to a noticeable degree.

摘要翻译： 公开了一种装载有晶体管，集成电路（IC）或LSI（大规模集成电路）的叠层印刷电路板及其制造方法。 电路板包括信号层，接地层和依次层叠有绝缘层中间的电源层。 在电源层中形成阻抗加法电路。 磁性层至少位于或至少使阻抗加法电路吹过。 具有这种配置的电路板可以显着降低电源噪声。

公开(公告)号：US06002593A

公开(公告)日：1999-12-14

申请号：US81137

申请日：1998-05-19

申请人： Hirokazu Tohya ,  Shiro Yoshida

发明人： Hirokazu Tohya ,  Shiro Yoshida

IPC分类号： H05K1/02 ,  H05K1/16 ,  H05K3/30 ,  H05K3/46

CPC分类号： H05K1/165 ,  H05K1/0233 ,  H05K1/0231 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/097 ,  H05K3/4688

摘要： A printed board has at least two conductor layers including a power supply layer and a ground layer, and a spiral coil inductor disposed in opposite ones of the conductor layers. The spiral coil inductor has a terminal connected to a power supply line of the power supply layer, and another terminal connected to a device power terminal disposed on one of the conductor layers and to be connected to a power supply terminal of a circuit device and a terminal of a decoupling capacitor. A device ground terminal is disposed on one of the conductor layers and to be connected to a ground terminal of the circuit device and another terminal of the decoupling capacitor, the device ground terminal being connected to a ground line of the ground layer.

摘要翻译： 印刷电路板具有包括电源层和接地层的至少两个导体层，以及布置在相对的导体层中的螺旋线圈电感器。 螺旋线圈电感器具有连接到电源层的电源线的端子，以及连接到设置在一个导体层上并连接到电路装置的电源端子的器件电源端子的另一端子，以及 去耦电容的端子。 器件接地端子设置在导体层中的一个上，并连接到电路器件的接地端子和去耦电容器的另一个端子，器件接地端子连接到接地层的接地线。

公开(公告)号：US5978231A

公开(公告)日：1999-11-02

申请号：US82800

申请日：1998-05-21

申请人： Hirokazu Tohya ,  Shiro Yoshida ,  Yuzo Shimada

发明人： Hirokazu Tohya ,  Shiro Yoshida ,  Yuzo Shimada

IPC分类号： H01F1/34 ,  H01F17/00 ,  H01F27/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  H05K7/06 ,  H05K9/00

CPC分类号： H01F17/0013 ,  H05K1/0233 ,  H05K1/165 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/097 ,  H05K3/4688

摘要： An insulative magnetic layer is disposed between a power source conductor layer and a ground conductor layer of a printed-wiring board. Two pieces of conductors are formed by cutting out a part of the power source conductor layer. Another two pieces of conductors are formed by cutting out a part of the ground conductor layer. The former conductors and the latter conductors are connected by five viaholes. A spiral coil inductor of a spiral form is formed in this way. This inductor has the strengthened inductance owing to the insulative magnetic layer provided therein.

摘要翻译： 绝缘磁性层设置在印刷电路板的电源导体层和接地导体层之间。 通过切掉电源导体层的一部分来形成两个导体。 通过切掉接地导体层的一部分来形成另外两个导体。 前导体和后导体通过五个通孔连接。 以这种方式形成螺旋形螺旋线圈电感器。 该电感器由于其中提供的绝缘磁性层而具有增强的电感。