利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

134 条记录 (耗时 0.03 秒)

    Nonvolatile semiconductor memory device with a row redundancy circuit
    2.
    发明授权
    Nonvolatile semiconductor memory device with a row redundancy circuit 失效
    具有行冗余电路的非易失性半导体存储器件

    公开(公告)号：US5548557A

    公开(公告)日：1996-08-20

    申请号：US179731

    申请日：1994-01-11

    申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

    摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

    摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

    Non-volatile semiconductor memory device
    5.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5283758A

    公开(公告)日：1994-02-01

    申请号：US794708

    申请日：1991-11-20

    申请人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

    发明人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

    IPC分类号： G11C7/18 ,  G11C16/04 ,  G11C16/16 ,  G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0425 ,  G11C16/0491 ,  G11C7/18

    摘要： A plurality of memory cell transistors having floating gates are disposed in a matrix in the direction of row and column to form a memory cell array. The memory cell array is divided into a plurality of sectors for every predetermined row. In each sector, sector selecting transistors and sub bit lines are provided, so that erasing and programming can be made for each sector. Therefore, total erasing for sector becomes possible, and since no voltage is applied to sub bit lines and word lines of non-selected sectors, the number of operations of preventing writing into non-selected memory cells is as many as the word lines included in one sector.

    摘要翻译： 具有浮动栅极的多个存储单元晶体管以行和列的方向设置在矩阵中以形成存储单元阵列。 存储单元阵列被划分成用于每个预定行的多个扇区。 在每个扇区中，提供扇区选择晶体管和子位线，从而可以对每个扇区进行擦除和编程。 因此，扇区的全部擦除成为可能，并且由于没有电压施加到非选择扇区的子位线和字线，所以防止写入未选择的存储单元的操作次数与包括在 一个部门。

    Nonvolatile semiconductor memory device and a writing method using electron tunneling
    6.
    发明授权
    Nonvolatile semiconductor memory device and a writing method using electron tunneling 失效
    非易失性半导体存储器件和使用电子隧穿的写入方法

    公开(公告)号：US4958317A

    公开(公告)日：1990-09-18

    申请号：US224743

    申请日：1988-07-27

    申请人： Yasushi Terada ,  Kazuo Kobayashi ,  Takeshi Nakayama

    发明人： Yasushi Terada ,  Kazuo Kobayashi ,  Takeshi Nakayama

    IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/10

    CPC分类号： G11C16/10

    摘要： Externally inputted data of one word line is temporarily stored in a latch circuit. In the writing cycle, the data stored and held in the latch circuit is collectively written in memory transistors connected to the selected word line. On this occasion, 0 V is applied to one of the control gate and the drain of the memory transistor in which "0" is written and a high voltage V.sub.PP is applied to the other of the control gate and the drain. Therefore, not only in the erasing cycle but also in the writing cycle, the operation is carried out by the movement of charges caused by the electron tunneling.

    摘要翻译： 一个字线的外部输入数据被临时存储在锁存电路中。 在写入周期中，存储并保持在锁存电路中的数据被共同地写入连接到所选字线的存储晶体管中。 在这种情况下，0V被施加到其中写入“0”的存储晶体管的控制栅极和漏极之一，并且高电压VPP被施加到控制栅极和漏极中的另一个。 因此，不仅在擦除循环中，而且在写入周期中，通过电子隧穿引起的电荷的移动来进行操作。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4694314A

    公开(公告)日：1987-09-15

    申请号：US811884

    申请日：1985-12-20

    申请人： Yasushi Terada ,  Takeshi Nakayama

    发明人： Yasushi Terada ,  Takeshi Nakayama

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

    CPC分类号： G11C16/12

    摘要： A semiconductor device in which a capacitor of a switched-capacitor included in an RC network for defining the rise time of a programming high-voltage pulse signal of an EEPROM is formed of an oxide film having a thickness corresponding to the thickness of a tunnel oxide film or an oxide film between a floating gate and a control gate so that a shift amount of a threshold voltage of a memory transistor is made constant even if the thickness of the tunnel oxide film or the oxide film between the floating gate and the control gate is deviated from a designed value.

    摘要翻译： 包括在RC网络中的用于限定EEPROM的编程高电压脉冲信号的上升时间的开关电容器的电容器的半导体器件由具有对应于隧道氧化物的厚度的厚度的氧化物膜形成 薄膜或浮动栅极和控制栅极之间的氧化物膜，使得即使隧道氧化物膜的厚度或浮动栅极和控制栅极之间的氧化物膜，存储晶体管的阈值电压的偏移量也变得恒定 偏离设计值。

    Nonvolatile semiconductor memory device
    9.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4813018A

    公开(公告)日：1989-03-14

    申请号：US125540

    申请日：1987-11-25

    申请人： Kazuo Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama

    发明人： Kazuo Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama

    IPC分类号： G11C17/00 ,  G11C14/00 ,  G11C16/04 ,  G11C7/00

    CPC分类号： G11C14/00

    摘要： A nonvolatile semiconductor memory device comprises a random access memory (RAM) and an electrically programmable and erasable read only memory (EEPROM). Since a capacitance (106) is formed between a control gate (103) and a drain (102) of a memory transistor, and a source of the memory transistor is rendered to be floating in the RAM write and read operation and in the EEPROM write operation and is supplied with a finite potential in EEPROM read operation, the operation of nonvolatile memory is achieved. A sense amplifier (15, 16) is amplified the potential difference between a bit line (BL) and a control gate line (CGL) is both memory operation and latches the input data in both write operation, such that the potential of the BL and the CGL are determined low or high potential. Besides in the EEPROM write operation, after latching the input data in the sense amplifier, a nonvolatile program is started such that a BL or a CGL is pumped up to program voltage (15-20 V). In the EEPROM read operation, a BL and a CGL are pre-changed in a different potential (BL CGL). After that, the sense amplifier is activated and the EEPROM data is read out.

    摘要翻译： 非易失性半导体存储器件包括随机存取存储器（RAM）和电可编程和可擦除只读存储器（EEPROM）。 由于在存储晶体管的控制栅极（103）和漏极（102）之间形成电容（106），并且存储晶体管的源极被浮置在RAM写入和读取操作中以及EEPROM写入 在EEPROM读操作中提供有限电位，实现非易失性存储器的操作。 读出放大器（15,16）被放大，位线（BL）和控制栅极线（CGL）之间的电位差都是存储器操作，并且在两个写操作中锁存输入数据，使得BL和 CGL被确定为低电位或高电位。 除了EEPROM写入操作之外，在将读出放大器中的输入数据锁存之后，启动非易失性程序，使BL或CGL被泵送到编程电压（15-20V）。 在EEPROM读取操作中，BL和CGL在相同电位（BL = CGL）均衡之后被预先改变为不同的电位（BL CGL）。 之后，激活读出放大器并读出EEPROM数据。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4691216A

    公开(公告)日：1987-09-01

    申请号：US811881

    申请日：1985-12-20

    申请人： Yasushi Terada ,  Takeshi Nakayama

    发明人： Yasushi Terada ,  Takeshi Nakayama

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

    CPC分类号： G11C16/30

    摘要： A semiconductor memory device in which an output of a reference voltage generator for defining the height of a programming high-voltage pulse is changed according to the thickness of a tunnel oxide film and/or a floating gate oxide film of a memory transistor so that a shift amount of a threshold voltage of an EEPROM is maintained at a constant value if the thickness of the oxide films is deviated from a designed value.

    摘要翻译： 一种半导体存储器件，其中用于限定编程高电压脉冲的高度的参考电压发生器的输出根据存储晶体管的隧道氧化物膜和/或浮栅氧化膜的厚度而改变，使得 如果氧化膜的厚度偏离设计值，则EEPROM的阈值电压的移位量保持恒定值。