公开(公告)号：US09229161B2

公开(公告)日：2016-01-05

申请号：US13729922

申请日：2012-12-28

申请人： Kenji Todori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tsukasa Tada ,  Ko Yamada ,  Shigehiko Mori ,  Naomi Shida ,  Reiko Yoshimura

发明人： Kenji Todori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Tsukasa Tada ,  Ko Yamada ,  Shigehiko Mori ,  Naomi Shida ,  Reiko Yoshimura

IPC分类号： G02B6/12 ,  G02B6/26 ,  G02B6/10 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/125

CPC分类号： G02B6/12 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1223 ,  G02B6/125

摘要： According to one embodiment, a waveguide includes: a substrate and a member. The member covers at least a part of the substrate and has a difference in the refractive index from the substrate not less than 2. A plurality of concave parts are provided on the substrate. The concave parts are arrayed on an upper face of the substrate. At least a part of a side face of each of the concave parts includes an arc. An inner diameter of each of the concave parts is not more than 50 nm. Intervals of the neighboring concave parts are not more than the inner diameter. The member fills the concave part.

摘要翻译： 根据一个实施例，波导包括：基板和部件。 该构件覆盖基板的至少一部分，并且其折射率与基板的折射率不同不小于2.在基板上设置多个凹部。 凹部排列在基板的上表面上。 每个凹部的侧面的至少一部分包括弧。 每个凹部的内径不大于50nm。 相邻凹部的间隔不大于内径。 构件填充凹部。

公开(公告)号：US08957501B2

公开(公告)日：2015-02-17

申请号：US13671077

申请日：2012-11-07

申请人： Takeshi Hioka ,  Yoshiaki Fukuzumi

发明人： Takeshi Hioka ,  Yoshiaki Fukuzumi

IPC分类号： H01L27/06 ,  H01L27/115 ,  H01L49/02

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L28/88

摘要： A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.

摘要翻译： 非易失性半导体存储装置包含存储单元区域，第一电极和第二电极。 存储单元区域形成在衬底上并且包括作为存储器串的一部分堆叠在衬底上的多个存储器单元。 多个第一导电层层叠在基板上。 第一电极用作电容部件一侧的电极，并且包括层叠在基板上的多个导电层，并且与设置在与第一电极相对的电容部件侧的第二电极的层叠导电层水平分离。

公开(公告)号：US08912594B2

公开(公告)日：2014-12-16

申请号：US13560260

申请日：2012-07-27

申请人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/105

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a second insulating layer, a select gate, a memory hole, a memory film, a channel body, a first semiconductor layer, and a second semiconductor layer. The select gate is provided on the second insulating layer. The memory film is provided on an inner wall of the memory hole. The channel body is provided inside the memory film. The first semiconductor layer is provided on an upper surface of the channel body. The second semiconductor layer is provided on the first semiconductor layer. The first semiconductor layer contains silicon germanium. The second semiconductor layer contains silicon germanium doped with a first impurity. A boundary between the first semiconductor layer and the second semiconductor layer is provided above a position of an upper end of the select gate.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括层叠体，第二绝缘层，选择栅极，存储器孔，存储​​膜，通道体，第一半导体层和第二半导体层。 选择栅极设置在第二绝缘层上。 记忆膜设置在存储孔的内壁上。 通道体设置在记忆膜的内部。 第一半导体层设置在通道主体的上表面上。 第二半导体层设置在第一半导体层上。 第一半导体层包含硅锗。 第二半导体层包含掺杂有第一杂质的硅锗。 第一半导体层和第二半导体层之间的边界设置在选择栅极的上端的位置的上方。

公开(公告)号：US08791464B2

公开(公告)日：2014-07-29

申请号：US12820371

申请日：2010-06-22

申请人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括堆叠结构，半导体柱，存储层和外部绝缘膜。 堆叠结构包括沿第一方向交替堆叠的多个电极膜和多个电极间绝缘膜。 半导体柱沿第一方向刺穿层叠结构。 存储层设置在电极膜和半导体柱之间。 外绝缘膜设置在电极膜和存储层之间。 该装置包括第一区域和第二区域。 沿着与第一区域的第一方向垂直的第二方向的外绝缘膜的外径大于第二区域的外径。 第一区域中沿着第二方向的外绝缘膜的厚度比第二区域厚。

公开(公告)号：US08653582B2

公开(公告)日：2014-02-18

申请号：US12724713

申请日：2010-03-16

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/788

CPC分类号： H01L27/11582 ,  H01L21/223 ,  H01L21/265 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于 第一方向 第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。

公开(公告)号：US08569133B2

公开(公告)日：2013-10-29

申请号：US13366509

申请日：2012-02-06

申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US08440528B2

公开(公告)日：2013-05-14

申请号：US12638480

申请日：2009-12-15

申请人： Masaru Kito ,  Masaru Kidoh ,  Tomoko Fujiwara ,  Yosuke Komori ,  Megumi Ishiduki ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

发明人： Masaru Kito ,  Masaru Kidoh ,  Tomoko Fujiwara ,  Yosuke Komori ,  Megumi Ishiduki ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/788 ,  G11C16/0458 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1156 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

摘要： A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.

摘要翻译： 非易失性半导体存储器件包括：通过交替堆叠多个层间绝缘膜和多个控制栅电极来形成堆叠体; 在层叠体中形成沿堆叠方向延伸的通孔; 通过通孔蚀刻面向通孔的层间绝缘膜的一部分以除去该部分; 形成去除部分; 在通孔的内表面和除去层间绝缘膜的部分之间形成第一绝缘膜; 在除去层间绝缘膜的部分中形成浮栅电极; 形成第二绝缘膜，以覆盖面对通孔的浮栅电极的一部分; 并将半导体柱埋在通孔中。

公开(公告)号：US20130113080A1

公开(公告)日：2013-05-09

申请号：US13671077

申请日：2012-11-07

申请人： Takeshi HIOKA ,  Yoshiaki Fukuzumi

发明人： Takeshi HIOKA ,  Yoshiaki Fukuzumi

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L28/88

摘要： A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.

摘要翻译： 非易失性半导体存储装置包含存储单元区域，第一电极和第二电极。 存储单元区域形成在衬底上并且包括作为存储器串的一部分堆叠在衬底上的多个存储器单元。 多个第一导电层层叠在基板上。 第一电极用作电容部件一侧的电极，并且包括层叠在基板上的多个导电层，并且与设置在与第一电极相对的电容部件侧的第二电极的层叠导电层水平分离。

公开(公告)号：US08372720B2

公开(公告)日：2013-02-12

申请号：US12679991

申请日：2008-12-09

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/513

摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US08361862B2

公开(公告)日：2013-01-29

申请号：US12714905

申请日：2010-03-01

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/28282 ,  H01L27/11582

摘要： A method for manufacturing a nonvolatile semiconductor memory device, the device including a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction and a semiconductor pillar piercing the stacked structural unit in the first direction, the method includes: forming a stacked unit including a core material film alternately stacked with a sacrificial film on a major surface of a substrate perpendicular to the first direction; making a trench in the stacked unit, the trench extending in the first direction and a second direction in a plane perpendicular to the first direction; filling a filling material into the trench; removing the sacrificial film to form a hollow structural unit, the hollow structural unit including a post unit supporting the core material film on the substrate, the post unit being made of the filling material; and forming the stacked structural unit by stacking one of the insulating films and one of the electrode films on a surface of the core material film exposed by removing the sacrificial film.

摘要翻译： 一种用于制造非易失性半导体存储器件的方法，该器件包括层叠结构单元，该堆叠结构单元包括在第一方向上交替堆叠多个电极膜的多个绝缘膜，以及沿第一方向穿透层叠结构单元的半导体柱， 方法包括：在垂直于第一方向的基板的主表面上形成包括交替堆叠有牺牲膜的芯材膜的堆叠单元; 在所述堆叠单元中形成沟槽，所述沟槽在垂直于所述第一方向的平面中沿所述第一方向延伸并且沿第二方向延伸; 将填充材料填充到沟槽中; 去除所述牺牲膜以形成中空结构单元，所述中空结构单元包括支撑所述芯材膜的柱单元，所述柱单元由所述填充材料制成; 以及通过将绝缘膜和其中一个电极膜层叠在通过去除牺牲膜而暴露的芯材膜的表面上来形成层叠结构单元。