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    Semiconductor integrated circuit having function for switching operational mode of internal circuit
    1.
    发明授权
    Semiconductor integrated circuit having function for switching operational mode of internal circuit 失效
    具有切换内部电路工作模式功能的半导体集成电路

    公开(公告)号：US4771407A

    公开(公告)日：1988-09-13

    申请号：US79061

    申请日：1987-07-29

    申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Hatsuo Miyahara ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada ,  Satoshi Momozono

    发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Hatsuo Miyahara ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada ,  Satoshi Momozono

    IPC分类号： H03K3/353 ,  G01R31/28 ,  G11C11/401 ,  G11C29/46 ,  G11C11/40

    CPC分类号： G11C29/46

    摘要： In a semiconductor integrated circuit having first and second power supply lines for receiving a power supply voltage, an external input terminal for receiving an input signal, and a high voltage detection circuit for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage, the high voltage detection circuit comprises an input circuit connected to the external input terminal for generating circuit for generating a reference voltage; and a differential voltage amplifier connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied, the input circuit comprising; a level shift element connected to the external input terminal for providing the detection voltage; an impedance element connected between the level shift element and the second power supply line; and a leak current compensating element connected between the first power supply line and the level shift element for allowing a current to flow from the first power supply line through the leak current compensating element and the impedance element to the second power supply line when the high voltage is not applied to the external input terminal.

    摘要翻译： 在具有用于接收电源电压的第一和第二电源线，用于接收输入信号的外部输入端子和用于在外部输入端子处检测高于预定电压的高电压的高电压检测电路的半导体集成电路中， 高电压检测电路包括连接到外部输入端的输入电路，用于产生用于产生参考电压的电路; 连接的差分电压放大器，用于接收检测电压和参考电压，用于放大检测电压和参考电压之间的差值，从而确定是否施加高电压，输入电路包括： 连接到所述外部输入端子以提供所述检测电压的电平移动元件; 连接在电平移位元件和第二电源线之间的阻抗元件; 以及泄漏电流补偿元件，其连接在所述第一电源线和所述电平移动元件之间，用于当高电压时允许电流从所述第一电源线流过所述漏电流补偿元件和所述阻抗元件流到所述第二电源线 不适用于外部输入端子。

    Semiconductor memory and burn-in test method of semiconductor memory
    3.
    发明授权
    Semiconductor memory and burn-in test method of semiconductor memory 有权
    半导体存储器的半导体存储器和老化测试方法

    公开(公告)号：US07200059B2

    公开(公告)日：2007-04-03

    申请号：US11260486

    申请日：2005-10-28

    申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

    发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

    IPC分类号： G11C29/00

    CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

    摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

    摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

    Semiconductor memory and burn-in test method of semiconductor memory
    4.
    发明申请
    Semiconductor memory and burn-in test method of semiconductor memory 有权
    半导体存储器的半导体存储器和老化测试方法

    公开(公告)号：US20060291307A1

    公开(公告)日：2006-12-28

    申请号：US11260486

    申请日：2005-10-28

    申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

    发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

    IPC分类号： G11C29/00

    CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

    摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

    摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

    NANOIMPRINT CURABLE COMPOSITION, NANOIMPRINT-LITHOGRAPHIC MOLDED PRODUCT, AND METHOD FOR FORMING PATTERN
    5.
    发明申请
    NANOIMPRINT CURABLE COMPOSITION, NANOIMPRINT-LITHOGRAPHIC MOLDED PRODUCT, AND METHOD FOR FORMING PATTERN 审中-公开
    纳米印刷可固化组合物，纳米压印成型产品和形成图案的方法

    公开(公告)号：US20140061970A1

    公开(公告)日：2014-03-06

    申请号：US13985792

    申请日：2012-02-14

    申请人： Hitoshi Sekine ,  Yasuhiro Takada ,  Hisashi Tanimoto ,  Naoto Yagi

    发明人： Hitoshi Sekine ,  Yasuhiro Takada ,  Hisashi Tanimoto ,  Naoto Yagi

    IPC分类号： G03F7/075 ,  G03F7/00

    CPC分类号： G03F7/0757 ,  B82Y10/00 ,  B82Y40/00 ,  C08F290/068 ,  C09D151/006 ,  G03F7/0002 ,  C08F222/1006

    摘要： The present invention provides a nanoimprint curable composition to be used in “nanoimprint lithography” in which a nanoimprint mold is pressed to transfer a fine concave-convex pattern, the nanoimprint curable composition containing a composite resin which has a polysiloxane segment and a polymer segment other than the polysiloxane segment, the polysiloxane segment containing a silanol group and/or hydrolyzable silyl group and having a polymerizable double bond. In addition, the present invention provides a nanoimprint-lithographic molded product, resist film, resin mold, and method for forming a pattern, which each involves use of the nanoimprint composition.

    摘要翻译： 本发明提供一种纳米压印光固化组合物，其中纳米压印模具被压制以转移细凹凸图案，纳米压印可固化组合物含有具有聚硅氧烷链段和聚合物链段的复合树脂 聚硅氧烷链段含有硅烷醇基和/或可水解甲硅烷基并具有可聚合双键。 另外，本发明提供纳米压印平版印刷成型体，抗蚀剂膜，树脂模具，以及形成图案的方法，每一种都使用纳米压印组合物。

    SURFACE-TREATED SUBSTRATE, LIGHT-RECEIVING-SIDE PROTECTIVE SHEET FOR SOLAR CELL USING THE SAME, AND SOLAR CELL MODULE
    6.
    发明申请
    SURFACE-TREATED SUBSTRATE, LIGHT-RECEIVING-SIDE PROTECTIVE SHEET FOR SOLAR CELL USING THE SAME, AND SOLAR CELL MODULE 审中-公开
    表面处理基板，使用其的太阳能电池的光接收侧保护片和太阳能电池模块

    公开(公告)号：US20120103398A1

    公开(公告)日：2012-05-03

    申请号：US13318545

    申请日：2010-05-19

    申请人： Tatsuo Kanou ,  Yasuhiro Takada ,  Shinichi Kudo ,  Takashi Yasumura

    发明人： Tatsuo Kanou ,  Yasuhiro Takada ,  Shinichi Kudo ,  Takashi Yasumura

    IPC分类号： H01L31/048 ,  C23C16/00 ,  C09D183/04

    CPC分类号： C08G77/442 ,  C08J7/047 ,  C08J7/12 ,  C08J2367/03 ,  C08J2483/04 ,  C09D183/10

    摘要： There is provided a surface-treated substrate obtained by forming a cured material layer composed of a resin composition on a surface of a substrate and then treating a surface of the cured material layer composed of the resin composition with a sulfur trioxide-containing gas, wherein the resin composition contains a composite resin (A) obtained by bonding a polysiloxane segment (a1) having a structural unit represented by general formula (1) and/or general formula (2) and a silanol group and/or a hydrolyzable silyl group to a vinyl-based polymer segment (a2) through a bond represented by general formula (3). There are also provided a light-receiving-side protective sheet for solar cells that uses the surface-treated substrate having a sheet shape and a solar cell module. The surface-treated substrate has good long-lasting antifouling properties.

    摘要翻译： 提供了一种表面处理基板，其通过在基板的表面上形成由树脂组合物构成的固化材料层，然后用含三氧化硫的气体处理由树脂组合物构成的固化材料层的表面，其中 树脂组合物含有通过将具有通式（1）和/或通式（2）表示的结构单元的聚硅氧烷链段（a1）与硅烷醇基和/或可水解甲硅烷基键合而得到的复合树脂（A） 通过通式（3）表示的键的乙烯基类聚合物链段（a2）。 还提供了一种使用具有片状形状的表面处理基板和太阳能电池模块的用于太阳能电池的光接收侧保护片。 经表面处理的基材具有良好的持久防污性能。

    PHOTOCATALYST-SUPPORTING SHEET AND PRIMER FOR PHOTOCATALYST-SUPPORTING SHEET
    9.
    发明申请
    PHOTOCATALYST-SUPPORTING SHEET AND PRIMER FOR PHOTOCATALYST-SUPPORTING SHEET 审中-公开
    光催化降解支撑片和光催化剂支撑片

    公开(公告)号：US20120077668A1

    公开(公告)日：2012-03-29

    申请号：US13260246

    申请日：2010-04-27

    申请人： Yasuhiro Takada ,  Hidekazu Miyano ,  Shinichi Kudo

    发明人： Yasuhiro Takada ,  Hidekazu Miyano ,  Shinichi Kudo

    IPC分类号： B01J31/06

    CPC分类号： C09D183/14

    摘要： A photocatalyst-supporting sheet includes at least an active energy ray-curable resin layer and a photocatalyst layer which are provided in that order on a substrate. The active energy ray-curable resin layer contains a composite resin (A) in which a polysiloxane segment (a1) and a vinyl polymer segment (a2) are bonded through a bond represented by general formula (3), the polysiloxane segment (a1) having a structural unit represented by general formula (1) and/or general formula (2) and having a silanol group and/or a hydrolyzable silyl group.

    摘要翻译： 光催化剂负载片材至少包括在基板上依次设置的活性能量射线固化树脂层和光催化剂层。 活性能量射线固化型树脂层含有通过通式（3）表示的键，聚硅氧烷链段（a1）与聚硅氧烷链段（a1）和乙烯基聚合物链段（a2）结合的复合树脂（A） 具有由通式（1）和/或通式（2）表示的具有硅烷醇基和/或可水解甲硅烷基的结构单元。