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    Bi-layer oxide ferroelectrics
    4.
    发明授权
    Bi-layer oxide ferroelectrics 失效
    双层氧化物铁电体

    公开(公告)号：US5914068A

    公开(公告)日：1999-06-22

    申请号：US765575

    申请日：1996-12-30

    申请人： Masahiko Hiratani ,  Keiko Kushida ,  Kazushige Imagawa ,  Kazumasa Takagi

    发明人： Masahiko Hiratani ,  Keiko Kushida ,  Kazushige Imagawa ,  Kazumasa Takagi

    IPC分类号： C04B35/453 ,  C30B29/22

    CPC分类号： C04B35/453

    摘要： Novel Bi-layer Perovskite ferroelectrics constituted of BiO intermediate layers (17) and pseudo-Perovskite layers (18) stacked alternately are disclosed. The Bi-layer Perovskite ferroelectrics have such a crystal structure which has a fundamental skeleton composed of each intermediate layer (17) consisting of one BiO plane and each pseudo-Perovskite structure (18) consisting of Pb(Zr, Ti)O.sub.3. Since the intermediate layer (17) is constituted of the BiO layer, the ferroelectrics are more excellent in ferroelectric characteristics and thermodynamic stability than known Perovskite ferroelectrics comprising a Bi.sub.2 O.sub.2 layer.

    摘要翻译： PCT No.PCT / JP95 / 01205 Sec。 371日期1996年12月30日第 102（e）日期1996年12月30日PCT归档1995年6月16日PCT公布。 出版物WO96 / 00704 日期1996年1月11日公开了由交替堆叠的BiO中间层（17）和伪钙钛矿层（18）构成的新型双层钙钛矿型铁电体。 双层钙钛矿铁电体具有这样的晶体结构，其具有由由一个BiO平面构成的每个中间层（17）和由Pb（Zr，Ti）O 3组成的每个假钙钛矿结构（18）组成的基本骨架。 由于中间层（17）由BiO层构成，所以铁电体的铁电特性和热力学稳定性优于包括Bi 2 O 2层的已知钙钛矿型铁电体。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06833577B2

    公开(公告)日：2004-12-21

    申请号：US10300763

    申请日：2002-11-21

    申请人： Yuichi Matsui ,  Masahiko Hiratani

    发明人： Yuichi Matsui ,  Masahiko Hiratani

    IPC分类号： H01L27108

    CPC分类号： H01L21/022 ,  C23C16/18 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31604 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75 ,  H01L28/90

    摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

    摘要翻译： 本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。 由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底部电极和阻挡金属的氧化。 然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。 因此，出现漏电流增加的问题。 作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化二钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。 通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。 通过电介质膜的多级形成，可以降低泄漏电流。

    Production of semiconductor integrated circuit
    7.
    发明授权
    Production of semiconductor integrated circuit 失效

    公开(公告)号：US06509246B2

    公开(公告)日：2003-01-21

    申请号：US09877207

    申请日：2001-06-11

    申请人： Hiroshi Miki ,  Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Tomoyuki Hamada

    发明人： Hiroshi Miki ,  Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Tomoyuki Hamada

    IPC分类号： H01L2120

    CPC分类号： H01L28/84 ,  H01L27/10814 ,  H01L28/91

    摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

    Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same
    8.
    发明授权
    Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same 有权
    具有多个DRAM存储单元的半导体器件及其制造方法

    公开(公告)号：US08106441B2

    公开(公告)日：2012-01-31

    申请号：US12861407

    申请日：2010-08-23

    申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

    发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

    IPC分类号： H01L27/06

    CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

    摘要翻译： DRAM的存储单元电容器（C3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同层（M3）的金属布线作为其电极，从而能够减少 工艺成本 通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。 此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。 通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

    SEMICONDUCTOR DEVICE HAVING PLURAL DRAM MEMORY CELLS AND A LOGIC CIRCUIT AND METHOD FOR MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING PLURAL DRAM MEMORY CELLS AND A LOGIC CIRCUIT AND METHOD FOR MANUFACTURING THE SAME 有权
    具有PLOR DRAM存储器单元的半导体器件和逻辑电路及其制造方法

    公开(公告)号：US20100314676A1

    公开(公告)日：2010-12-16

    申请号：US12861407

    申请日：2010-08-23

    申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

    发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

    摘要翻译： DRAM的存储单元电容器（C3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同层（M3）的金属布线作为其电极，从而能够减少 工艺成本 通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。 此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。 通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。