公开(公告)号：US4984055A

公开(公告)日：1991-01-08

申请号：US267103

申请日：1988-11-07

申请人： Yoshinori Okumura ,  Atsuhiro Fujii ,  Masao Nagatomo ,  Hiroji Ozaki ,  Wataru Wakamiya ,  Takayuki Matsukawa

发明人： Yoshinori Okumura ,  Atsuhiro Fujii ,  Masao Nagatomo ,  Hiroji Ozaki ,  Wataru Wakamiya ,  Takayuki Matsukawa

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L23/485 ,  H01L23/522 ,  H01L2924/0002

摘要： A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15). Each of the three insulating layers in the triple layer insulation has its hole-defining surface exposed at the contact hole (15) flush with or displaced laterally into the contact hole (15) away from a corresponding hole-defining exposed surface of the next overlying insulating layer.

摘要翻译： 公开了具有多个导电层的半导体器件。 该器件具有在半导体衬底（1）上间隔开形成的第一级导体（9）。 半导体衬底（1）在相邻的第一层导体（9）之间的主表面上设置有杂质扩散区（11）。 由一对氧化物层（12,14）和夹在氧化物层（12,14）之间的氧化硅层（13）形成的三层绝缘体覆盖在其上的半导体衬底（1）和第一层导体（9） 。 形成至少一个接触孔（15），以通过三层绝缘体延伸到半导体衬底（1）中的杂质扩散区域（11）或半导体衬底（1）上的第一级导体（9）中。 在三层绝缘体和接触孔（15）的内周围壁上设置有二级导体（16,17）。 三层绝缘体中的三个绝缘层中的每一个具有其露出在接触孔（15）处的孔限定表面，该接触孔（15）与接触孔（15）平齐地或相对地偏离接触孔（15），远离与下一个上覆的相应的孔限定的暴露表面 绝缘层。

公开(公告)号：US4956692A

公开(公告)日：1990-09-11

申请号：US266704

申请日：1988-11-03

申请人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

发明人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

IPC分类号： H01L27/10 ,  H01L21/31 ,  H01L21/334 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L21/76205 ,  H01L27/10829

摘要： Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.

摘要翻译： 在半导体衬底的主表面上以预定距离形成两个沟槽。 在包括沟槽的内表面的半导体的主表面上依次形成氧化物膜和氮化物膜。 在包括沟槽的内表面的整个表面上形成抗蚀剂之后，将抗蚀剂图案化以在每个沟槽的侧表面上暴露出氮化膜的一部分。 通过使用图案化的抗蚀剂作为掩模去除氮化物膜的暴露部分并施加热氧化。 然后，在沟槽之间的区域上形成隔离氧化膜，并且鸟嘴的端部位于每个沟槽的侧表面上并连接到形成在每个沟槽中的氧化膜。

公开(公告)号：US5097310A

公开(公告)日：1992-03-17

申请号：US409379

申请日：1989-09-19

申请人： Takahisa Eimori ,  Wataru Wakamiya ,  Hiroji Ozaki ,  Yoshinori Tanaka ,  Shinichi Satoh

发明人： Takahisa Eimori ,  Wataru Wakamiya ,  Hiroji Ozaki ,  Yoshinori Tanaka ,  Shinichi Satoh

IPC分类号： H01L21/761 ,  H01L21/76 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L27/0928

摘要： A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.

摘要翻译： 具有改进的隔离装置能力的互补半导体器件包括在衬底1的主表面上彼此相邻形成的P阱3和N阱2，形成在主衬底1上的P阱8中的N型杂质层 在基板的主表面上形成在N阱9中的P型杂质层，形成在基板主表面上的N阱和P阱71的接合部的N型区域， 第一屏蔽电极52，其通过绝缘膜形成在基板的主表面上的N型杂质层8和N型区域71之间，形成在N型区域71和P型杂质层9之间的第二屏蔽电极51， 基板的主表面通过绝缘膜。 第一屏蔽电极52连接到电位VSS，第二屏蔽电极51和N型区域71连接到电位VCC，使得包括第一屏蔽电极52的N沟道MOS晶体管101不导通， 包括第二屏蔽电极的装置不形成场效应晶体管。

公开(公告)号：US5084752A

公开(公告)日：1992-01-28

申请号：US538817

申请日：1990-06-15

申请人： Shinichi Satoh ,  Hiroji Ozaki ,  Hiroshi Kimura ,  Wataru Wakamiya ,  Yoshinori Tanaka

发明人： Shinichi Satoh ,  Hiroji Ozaki ,  Hiroshi Kimura ,  Wataru Wakamiya ,  Yoshinori Tanaka

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/85205 ,  H01L24/45 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025

摘要： A semiconductor device includes a substrate (4) in a periphery of which are formed elements isolating regions. A bonding pad (3) is formed above the elements isolating region, with an isolation layer (7) provided therebetween. An underlying layer (12) having a buffering function is formed on a surface of the bonding pad and the semiconductor substrate. In one aspect of the invention, wherein the elements isolating region is formed of LOCOS film (30), the underlying layer is formed between the bonding pad and the LOCOS film. In another aspect of the invention, the elements isolating region is of a field-shield structure (13, 14), and the underlying layer (12) is formed by separating a part of a gate electrode layer (14) of the field shield into an island. The underlying layer buffers the structure against an external force that is applied on the bonding pad in a bonding processing, to thereby prevent generation of cracks in the semiconductor layer.

摘要翻译： 半导体器件包括其周边的衬底（4），其形成有元件隔离区域。 在元件隔离区域的上方形成接合焊盘（3），其间设有隔离层（7）。 在接合焊盘和半导体衬底的表面上形成具有缓冲功能的下层（12）。 在本发明的一个方面，其中元件隔离区由LOCOS膜（30）形成，下层在接合焊盘和LOCOS膜之间形成。 在本发明的另一方面，元件隔离区域是场屏蔽结构（13,14），并且下层（12）是通过将场屏蔽的栅极电极层（14）的一部分分成 一个岛屿。 底层在结合处理中抵抗施加在接合焊盘上的外力缓冲结构，从而防止在半导体层中产生裂纹。

公开(公告)号：US5225704A

公开(公告)日：1993-07-06

申请号：US614963

申请日：1990-11-19

申请人： Wataru Wakamiya ,  Shinichi Satoh ,  Hiroji Ozaki ,  Takahisa Eimori ,  Yoshinori Tanaka

发明人： Wataru Wakamiya ,  Shinichi Satoh ,  Hiroji Ozaki ,  Takahisa Eimori ,  Yoshinori Tanaka

IPC分类号： H01L27/108

CPC分类号： H01L27/10805

摘要： In a DRAM having stacked capacitor cells, elements are isolated by field shield isolating structure. The field shield isolating structure is formed surrounding both X and Y directions of the memory cell in the DRAM. The field shield isolating structure comprises an isolating electrode layer formed on a semiconductor substrate between adjacent memory cells with an insulating film interposed therebetween. Two impurity regions included in the adjacent memory cells and the isolating electrode layer constitute a MOS transistor. A voltage for maintaining the MOS transistor normally-off is applied to the isolating electrode layer. A portion of the stacked capacitor extends to the isolating electrode layer. One of the source/drain regions of the MOS transistor is formed in self-alignment, using a sidewall spacer formed of an insulating film on a sidewall of the field shield electrode as a mask.

摘要翻译： 在具有层叠电容器单元的DRAM中，通过场屏蔽隔离结构来隔离元件。 在DRAM中的存储单元的X和Y方向上形成场屏蔽隔离结构。 场屏蔽隔离结构包括在相邻的存储单元之间的半导体衬底上形成有绝缘膜的隔离电极层。 包括在相邻存储单元和隔离电极层中的两个杂质区构成MOS晶体管。 用于保持MOS晶体管常闭的电压被施加到隔离电极层。 层叠电容器的一部分延伸到隔离电极层。 使用由场屏蔽电极的侧壁上的绝缘膜形成的侧壁间隔作为掩模，自对准地形成MOS晶体管的源/漏区之一。

公开(公告)号：US5181094A

公开(公告)日：1993-01-19

申请号：US783029

申请日：1991-10-25

申请人： Takahisa Eimori ,  Wataru Wakamiya ,  Hiroji Ozaki ,  Yoshinori Tanaka ,  Shinichi Satoh

发明人： Takahisa Eimori ,  Wataru Wakamiya ,  Hiroji Ozaki ,  Yoshinori Tanaka ,  Shinichi Satoh

IPC分类号： H01L27/092

CPC分类号： H01L27/0928 ,  H01L2924/0002

摘要： A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.

摘要翻译： 具有改进的隔离装置能力的互补半导体器件包括在衬底1的主表面上彼此相邻形成的P阱3和N阱2，形成在主衬底1上的P阱8中的N型杂质层 在基板的主表面上形成在N阱9中的P型杂质层，形成在基板主表面上的N阱和P阱71的接合部的N型区域， 第一屏蔽电极52通过绝缘膜形成在基板的主表面上的N型杂质层8和N型区域71之间，形成在N型区域71和P型杂质层9之间的第二屏蔽电极51 基板的主表面通过绝缘膜。 第一屏蔽电极52连接到电位VSS，第二屏蔽电极51和N型区域71连接到电位VCC，使得包括第一屏蔽电极52的N沟道MOS晶体管101不导通， 包括第二屏蔽电极的装置不形成场效应晶体管。

公开(公告)号：US5094965A

公开(公告)日：1992-03-10

申请号：US606276

申请日：1990-10-31

申请人： Hiroji Ozaki ,  Takahisa Eimori ,  Yoshinori Tanaka ,  Wataru Wakamiya ,  Shinichi Satoh

发明人： Hiroji Ozaki ,  Takahisa Eimori ,  Yoshinori Tanaka ,  Wataru Wakamiya ,  Shinichi Satoh

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/417

CPC分类号： H01L29/41775 ,  H01L27/10808

摘要： A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.

公开(公告)号：US4998161A

公开(公告)日：1991-03-05

申请号：US446560

申请日：1989-12-05

申请人： Hiroshi Kimura ,  Shinichi Satoh ,  Hiroji Ozaki ,  Yoshinori Tanaka ,  Wataru Wakamiya

发明人： Hiroshi Kimura ,  Shinichi Satoh ,  Hiroji Ozaki ,  Yoshinori Tanaka ,  Wataru Wakamiya

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/402 ,  H01L27/10805

摘要： In an element forming region (10) of a semiconductor substrate (1), there are provided a gate electrode (2), sidewall insulating films (4), impurity diffusion regions (5a and 5b) of a lower concentration having their one ends are overlapped with the side sections of the gate electrode (2), and impurity diffusion regions (6a and 6b) of a higher concentration having their one ends are overlapped with the side sections of the sidewall insulating films (4). In an element isolation region (7) of the semiconductor substrate, there are formed an electrostatic screening electrode (31) for element isolation and an insulating film (30) substantially enclosing the electrostatic screening electrode. By employing the electrostatic screening electrode (31) for element isolation in the LDD MOS transistor, there is obtained a semiconductor device of high performance and reliability which is free from intrusion of impurities from the element isolation region.

摘要翻译： 在半导体衬底（1）的元件形成区域（10）中，设置有栅电极（2），侧壁绝缘膜（4），具有其一端的较低浓度的杂质扩散区域（5a和5b） 与栅极（2）的侧部重叠，并且具有一端的较高浓度的杂质扩散区（6a和6b）与侧壁绝缘膜（4）的侧部重叠。 在半导体衬底的元件隔离区域（7）中，形成用于元件隔离的静电屏蔽电极（31）和基本上包围静电屏蔽电极的绝缘膜（30）。 通过在LDD MOS晶体管中采用用于元件隔离的静电屏蔽电极（31），可以获得高性能和可靠性的半导体器件，其不会从元件隔离区域侵入杂质。

公开(公告)号：US5180683A

公开(公告)日：1993-01-19

申请号：US727781

申请日：1991-07-10

申请人： Wataru Wakamiya ,  Yoshinori Tanaka ,  Takahisa Eimori ,  Hiroji Ozaki ,  Hiroshi Kimura ,  Shinichi Satoh

发明人： Wataru Wakamiya ,  Yoshinori Tanaka ,  Takahisa Eimori ,  Hiroji Ozaki ,  Hiroshi Kimura ,  Shinichi Satoh

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor had various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

摘要翻译： 根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。 堆叠的电容器堆叠在半导体衬底的表面上。 此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。 电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。 这些形状通过采用各种蚀刻工艺制成。 下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

公开(公告)号：US5177571A

公开(公告)日：1993-01-05

申请号：US425017

申请日：1989-10-23

申请人： Shinichi Satoh ,  Wataru Wakamiya ,  Takahisa Eimori ,  Hiroji Ozaki ,  Yoshinori Tanaka

发明人： Shinichi Satoh ,  Wataru Wakamiya ,  Takahisa Eimori ,  Hiroji Ozaki ,  Yoshinori Tanaka

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/42376 ,  H01L29/7836

摘要： Disclosed is an LDDMOSFET, in which a gate electrode (2) having a cross-sectional shape having a lower side and an upper side longer than the upper side is formed of only conductive materials, and diffusion layers (5b, 6b) of low concentration and high concentration constituting a drain are both formed so as to be overlapped with portions below the gate electrode (2) utilizing the shape of this gate electrode (2). Since the gate electrode (2) is formed of only the conductive materials, it becomes easy to word the gate electrode (2) so as to be in a desired shape. Since the diffusion layers (5b, 6b) of low concentration and high concentration constituting the drain are both overlapped with the portions below the gate electrode (2), the performance as a transistor is not degraded even if the polarity of the surface of the diffusion layer (5b, 6b) of low concentration is inverted by the effect of hot electrons.

摘要翻译： 公开了一种LDDMOSFET，其中具有仅具有导电材料的具有下侧且上侧比上侧更长的截面形状的栅电极（2）和低浓度的扩散层（5b，6b） 并且构成漏极的高浓度都利用该栅电极（2）的形状形成为与栅电极（2）下方的部分重叠。 由于栅电极（2）仅由导电材料形成，容易使栅电极（2）成为期望的形状。 由于构成漏极的低浓度和高浓度的扩散层（5b，6b）都与栅电极（2）下方的部分重叠，因此即使扩散表面的极性，晶体管的性能也不会降低 低浓度的层（5b，6b）由热电子的作用而反转。