公开(公告)号：US4713679A

公开(公告)日：1987-12-15

申请号：US787116

申请日：1985-10-15

申请人： Yoshio Terasawa ,  Saburo Oikawa

发明人： Yoshio Terasawa ,  Saburo Oikawa

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/744 ,  H01L29/74 ,  H01L29/80

CPC分类号： H01L29/744 ,  H01L29/0688 ,  H01L29/0834 ,  H01L29/36

摘要： A reverse blocking type semiconductor device capable of being rapidly turned off is disclosed in which a semiconductor substrate includes four semiconductor layers in a region sandwiched between a pair of principal surfaces in such a manner that adjacent ones of these layers are different in conductivity type from each other, one outermost layer of the layers is surrounded by the layer adjacent to the one outermost layer, the one outermost layer and the layer adjacent thereto are exposed to one principal surface, a cathode electrode kept in low-resistance contact with one outermost layer, a gate electrode is kept in low-resistance contact with the layer adjacent to the one outermost layer and lies in close proximity to the one outermost layer, an anode electrode is kept in low-resistance contact with the other outermost layer at the other principal surface, and a main operating region of the other outermost layer has an impurity concentration gradient in a direction parallel to the anode electrode.

摘要翻译： 公开了一种能够快速关闭的反向阻挡型半导体器件，其中半导体衬底在夹在一对主表面之间的区域中包括四个半导体层，使得这些层中的相邻层之间的导电类型不同于每个 另一方面，层的一个最外层被邻近一个最外层的层包围，一个最外层和与其相邻的层暴露于一个主表面，与一个最外层保持低电阻接触的阴极电极， 栅电极与邻近一个最外层的层保持低电阻接触，并且位于一个最外层附近，阳极电极与另一个主表面处的另一个最外层保持低电阻接触 ，另一个最外层的主工作区域在与ano平行的方向上具有杂质浓度梯度 电极。

公开(公告)号：US4514747A

公开(公告)日：1985-04-30

申请号：US357594

申请日：1982-03-12

申请人： Kenji Miyata ,  Yoshio Terasawa ,  Saburo Oikawa ,  Susumu Murakami ,  Masahiro Okamura

发明人： Kenji Miyata ,  Yoshio Terasawa ,  Saburo Oikawa ,  Susumu Murakami ,  Masahiro Okamura

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/744 ,  H01L29/74

CPC分类号： H01L29/744 ,  H01L29/0834 ,  H01L29/1066

摘要： Disclosed is a field controlled thyristor in which a first semiconductor region of N.sup.+ -type, a second semiconductor region of N-type, third semiconductor regions of P-type, a fourth semiconductor region of N.sup.- -type and a fifth semiconductor region of P.sup.+ -type are formed in a semiconductor substrate having two main surfaces, the first, second and third semiconductor regions being exposed in the first main surface and the fifth semiconductor region being exposed in the second main surface; and the third semiconductor regions of P-type are spaced from each other by a predetermined spacing. The third semiconductor regions are connected with surface-exposed semiconductor regions exposed in the first main surface. The impurity concentration in the second semiconductor region decreases from the first semiconductor region toward the third semiconductor region so that a low forward voltage drop can be achieved along with a high reverse blocking voltage. Also disclosed is a method for forming the third semiconductor regions and the surface-exposed semiconductor regions through a diffusion process alone.

摘要翻译： 公开了一种场控晶闸管，其中N +型的第一半导体区域，N型的第二半导体区域，P型的第三半导体区域，N型的第四半导体区域和P + 型形成在具有两个主表面的半导体衬底中，第一，第二和第三半导体区域暴露在第一主表面中，第五半导体区域暴露在第二主表面中; 并且P型的第三半导体区域彼此隔开预定间隔。 第三半导体区域与暴露在第一主表面中的暴露表面的半导体区域连接。 第二半导体区域中的杂质浓度从第一半导体区域朝向第三半导体区域减小，从而可以实现高反向阻断电压的低正向压降。 还公开了通过单独的扩散处理形成第三半导体区域和表面暴露的半导体区域的方法。

公开(公告)号：US4329772A

公开(公告)日：1982-05-18

申请号：US134673

申请日：1980-03-27

申请人： Saburo Oikawa ,  Susumu Murakami ,  Yoshio Terasawa

发明人： Saburo Oikawa ,  Susumu Murakami ,  Yoshio Terasawa

IPC分类号： H01L21/20 ,  H01L29/10 ,  H01L29/739 ,  H01L29/744 ,  H01L29/80 ,  H01L21/223

CPC分类号： H01L29/7392 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/1066 ,  H01L29/744 ,  H01L29/80 ,  Y10S148/026 ,  Y10S148/088

摘要： Disclosed is an improved method of growing an epitaxial layer preventing auto-doping from a doped region exposed to a surface of a semiconductor substrate. A surface of a semiconductor substrate of one conductivity type is covered with a mask having a predetermined opening. Then, impurity atoms are doped into the substrate through the opening to form a region of the other conductivity type. An epitaxial layer of one conductivity type is deposited over the exposed surface of the substrate with another mask which covers the entire surface of the region and has an area larger than that of the exposed surface of the region. The latter mask prevents auto-doping from the region of the other conductivity type. The process is usable for controlling, for example, channel widths of field effect semiconductor devices uniformly and precisely.

摘要翻译： 公开了一种生长外延层的改进方法，该外延层防止从暴露于半导体衬底的表面的掺杂区域进行自掺杂。 一种导电类型的半导体衬底的表面被具有预定开口的掩模覆盖。 然后，通过开口将杂质原子掺杂到衬底中以形成另一种导电类型的区域。 一种导电类型的外延层沉积在衬底的暴露表面上，另一个掩模覆盖该区域的整个表面并且具有比该区域的暴露表面大的面积。 后一种掩模阻止了从另一种导电类型的区域的自动掺杂。 该过程可用于均匀且精确地控制场效应半导体器件的通道宽度。

公开(公告)号：US4354121A

公开(公告)日：1982-10-12

申请号：US284794

申请日：1981-07-10

申请人： Yoshio Terasawa ,  Kenji Miyata ,  Saburo Oikawa ,  Susumu Murakami ,  Masahiro Okamura ,  Takuzo Ogawa

发明人： Yoshio Terasawa ,  Kenji Miyata ,  Saburo Oikawa ,  Susumu Murakami ,  Masahiro Okamura ,  Takuzo Ogawa

IPC分类号： H01L27/08 ,  H01L29/739 ,  H02M1/08 ,  H03K17/04 ,  H03K17/12 ,  H03K17/72 ,  H03K17/73 ,  H03K17/60

CPC分类号： H01L29/7392 ,  H01L27/0817 ,  H02M1/08 ,  H03K17/0406 ,  H03K17/125 ,  H03K17/72

摘要： A switching control circuit includes a first field controlled thyristor having a gate and a cathode between which a backward bias voltage source and a second field controlled thyristor are connected in series. Conduction of the second field controlled thyristor is controlled by controlling a voltage applied across the gate and the cathode, thereby to control conduction of the first field controlled thyristor. A large load current can be positively and safely turned on and off by a relatively small control current or voltage.

摘要翻译： 开关控制电路包括具有栅极和阴极的第一场控制晶闸​​管，在其间串联连接反向偏置电压源和第二场控制晶闸​​管。 通过控制施加在栅极和阴极两端的电压来控制第二场控晶闸管的导通，从而控制第一场控制晶闸​​管的导通。 通过相对较小的控制电流或电压可以正确安全地打开和关闭大负载电流。

公开(公告)号：US06180965B2

公开(公告)日：2001-01-30

申请号：US09068749

申请日：1998-07-02

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L2970

CPC分类号： H01L29/66356 ,  H01L29/66416 ,  H01L29/7392 ,  H01L29/7722

摘要： In a static induction semiconductor device, particular a high power static induction semiconductor device, recessed portions 12 are formed in one surface of a silicon substrate 11 of one conductivity type, gate regions 13 of the other conductivity type are formed at bottoms of the recessed portions, recessed portions 14 are formed at portions surrounded by adjacent gate regions, cathode short-circuit regions 15 of the other conductivity type are formed as an island at bottoms of the recessed portions to be extended to the surface of the silicon substrate. Cathode regions 17 extending up to the surface of the silicon substrate in succession to channel regions 16 surrounded by the cathode regions 13 and cathode short-circuit regions 15, are formed. A cathode electrode substrate 21 is formed to be contacted with the cathode short-circuit regions 15 and cathode regions 17. Carriers remaining within the channel regions at a turn-off are directly swept out into the cathode electrode substrate 21 through the cathode short-circuit regions 15, and thus it is possible to provide a static induction semiconductor device, in which a large current can be cut off at a high speed without increasing an on-resistance.

摘要翻译： 在静电感应半导体装置中，特别是高功率静电感应半导体装置，在一个导电型的硅衬底11的一个表面上形成凹部12，另一导电型的栅极区13形成在凹部的底部 在由相邻的栅极区域包围的部分形成有凹部14，另外的导电型的阴极短路区域15形成为在硅基板的表面延伸的凹部的底部的岛状。 形成由阴极区域13和阴极短路区域15围绕的沟道区域16连续延伸至硅衬底表面的阴极区域17。 阴极电极基板21形成为与阴极短路区域15和阴极区域17接触。残留在通道区域内的关闭的载流子通过阴极短路直接扫出阴极电极基板21 区域15，因此可以提供静电感应半导体器件，其中可以高速切断大电流而不增加导通电阻。

公开(公告)号：US6075269A

公开(公告)日：2000-06-13

申请号：US68718

申请日：1998-07-02

申请人： Yoshio Terasawa ,  Takayuki Sekiya

发明人： Yoshio Terasawa ,  Takayuki Sekiya

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L29/739 ,  H01L29/744 ,  H01L29/78

CPC分类号： H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/7392

摘要： A semiconductor device that includes a recessed portion formed by isotropic-etching through an opening in an oxide layer on a surface of the semiconductor substrate, an opening formed in an oxide layer formed on the inner surface of the recessed portion by anisotropic etching, a recessed portion formed adjacent another recessed portion by isotropic etching through the opening. An overhang portion in the oxide layers at the opening is used as a mask in successive etching steps, and the isotropic and anistropic etching steps are repeated through the same mask, to eliminate errors in stacking masks and obtaining a deep notched gate structure within a short period. A cross-sectional shape of the recessed portion includes a plurality of curved recessed portions of different curvatures. A semiconductor device thus formed includes a recessed portion having a high aspect (length/width) ratio, and a depth larger than the width.

摘要翻译： PCT No.PCT / JP97 / 03324 Sec。 371日期：1998年7月2日 102（e）1998年7月2日PCT PCT 1997年9月19日PCT公布。 公开号WO98 / 12756 日期：1998年3月26日一种半导体器件，其包括通过各向同性蚀刻形成的凹部，该凹部通过半导体衬底的表面上的氧化物层中的开口形成，形成在通过凹部的内表面形成在氧化物层中的开口， 各向异性蚀刻，通过各向同性蚀刻通过开口形成在另一凹部上的凹部。 在连续蚀刻步骤中，在开口处的氧化物层中的突出部分用作掩模，并且通过相同的掩模重复各向同性和不透明蚀刻步骤，以消除堆叠掩模中的错误并在短时间内获得深刻蚀栅极结构 期。 凹部的截面形状包括具有不同曲率的多个弯曲凹部。 这样形成的半导体器件包括具有高方位（长/宽）比和大于宽度的深度的凹部。

公开(公告)号：US5930651A

公开(公告)日：1999-07-27

申请号：US814787

申请日：1997-03-10

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L21/329 ,  H01L29/06 ,  H01L29/739 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L29/66356 ,  H01L29/0692 ,  H01L29/7392

摘要： A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate are ultrasonically cleaned to remove impurities therefrom, then cleaned by pure water, and dried by a spinner. Then, while lands on the upper surface of the N.sup.- substrate are being held against the surface of the N.sup.- substrate, the N.sup.- substrates are joined to each other by heating them at 800.degree. C. in a hydrogen atmosphere.

摘要翻译： 在N基板的下表面上形成P +层，在N基板的上表面形成有凹部。 然后，在凹部的侧壁和底部形成有P +栅极区域和底部栅极区域。 超声波清洗N-底物和N-底物以除去杂质，然后用​​纯水清洗，并用旋转器干燥。 然后，在N基板的上表面上的平台被保持在N基板的表面上的同时，通过在氢气气氛中在800℃下加热它们而将N基板彼此接合。

公开(公告)号：US5894140A

公开(公告)日：1999-04-13

申请号：US483589

申请日：1995-06-07

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/744 ,  H01L21/329 ,  H01L21/331 ,  H01L21/332 ,  H01L21/336 ,  H01L29/739 ,  H01L29/74 ,  H01L29/772 ,  H01L29/78 ,  H01L31/111

CPC分类号： H01L29/66356 ,  H01L29/66348 ,  H01L29/66378 ,  H01L29/7392 ,  H01L29/7722

摘要： A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is brought into contact with the surface of the first semiconductor substrate. The gate structure may be formed such that each of the recessed portions is completely or partially filled with the gate structure. When the gate structure includes electrically good-conductive films of a high melting point metal or the like each formed in respective one of the recessed portions, the gate resistance can be further decreased.

摘要翻译： 一种栅极结构，其包括各自具有高杂质浓度的半导体区域，并且形成在设置在第一半导体衬底的表面中的凹部中的相应一个中，然后使第二半导体衬底与第一半导体衬底的表面接触 。 栅极结构可以形成为使得每个凹部完全或部分地填充有栅极结构。 当栅极结构包括形成在各个凹部中的高熔点金属等的导电性良好的导电膜时，可以进一步降低栅极电阻。

公开(公告)号：US5847417A

公开(公告)日：1998-12-08

申请号：US516405

申请日：1995-08-17

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/74 ,  H01L21/329 ,  H01L29/739 ,  H01L29/80

CPC分类号： H01L29/66356 ,  H01L29/7392

摘要： A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P.sup.+ layer in a lower surface of an N.sup.- substrate, selectively forming P.sup.+ gate regions in an upper surface of the N.sup.- substrate, forming intergate P.sup.+ regions in the upper surface of the N.sup.- substrate between the P.sup.+ gate regions, forming an N.sup.+ layer in an upper surface of an N.sup.- substrate, joining the N.sup.- substrate and the N.sup.- substrate to each other by heating them at about 800.degree. C. in a hydrogen atmosphere while the upper surface of the N.sup.- substrate and a lower surface of the N.sup.- substrate are being held against each other, and forming an anode electrode and a cathode electrode.

摘要翻译： 通过在N基板的下表面中形成P +层，在N基板的上表面中选择性地形成P +栅极区域，制造在高品质基底上形成有栅极区域的常关半导体器件，形成栅极 P +栅极区域之间的N衬底的上表面中的P +区域，在N衬底的上表面中形成N +层，通过将N-衬底和N衬底彼此加热，以约800 在N基板的上表面和N基板的下表面彼此保持的同时，形成阳极电极和阴极电极。

公开(公告)号：US5950075A

公开(公告)日：1999-09-07

申请号：US955818

申请日：1997-10-22

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L29/739 ,  H01L29/74 ,  H01L29/744 ,  H01L21/332

CPC分类号： H01L29/744 ,  H01L29/7392

摘要： In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.

摘要翻译： 在一种导电类型的硅衬底的表面中，形成多个凹陷或凹陷，在各个凹部的底部形成相反导电类型的栅极区，在各个栅极区上设置栅电极，并且导电块 连接到半导体衬底的表面。 在半导体衬底的表面和导电块之间可以提供具有高杂质浓度的接触区域和/或导电材料层，以便改善半导体衬底与导电之间的接触的电学和机械性能 块。 栅极区域可以具有高杂质浓度，并且沟道区域和导电块之间的距离可以非常小。